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    High dielectric film and related method of manufacture
    2.
    发明授权
    High dielectric film and related method of manufacture 有权
    高介电膜及相关制造方法

    公开(公告)号：US07521331B2

    公开(公告)日：2009-04-21

    申请号：US11359404

    申请日：2006-02-23

    申请人： Hong-bae Park ,  Yu-gyun Shin ,  Sang-bom Kang

    发明人： Hong-bae Park ,  Yu-gyun Shin ,  Sang-bom Kang

    IPC分类号： H01L21/76

    CPC分类号： H01L21/0228 ,  C23C16/308 ,  C23C16/45531 ,  H01L21/02142 ,  H01L21/02194 ,  H01L21/02274 ,  H01L21/3141 ,  H01L21/3145 ,  H01L21/31645

    摘要： A method of forming a high dielectric film for a semiconductor device comprises supplying a first source gas to a reaction chamber during a first time interval, supplying a first reactant gas to the reaction chamber during a second time interval after the first time interval, supplying a second source gas to the reaction chamber for a third time interval after the second time interval, supplying a second reactant gas to the reaction chamber for a fourth time interval after the third time interval, and supplying an additive gas including nitrogen to the reaction chamber during a fifth time interval.

    摘要翻译： 形成用于半导体器件的高电介质膜的方法包括：在第一时间间隔内将第一源气体供应到反应室，在第一时间间隔之后的第二时间间隔期间将第一反应气体供应到反应室， 在所述第二时间间隔之后的第三时间间隔内将第二源气体供应到所述反应室，在所述第三时间间隔之后，将第二反应气体供应到所述反应室中第四时间间隔，并且在所述第三时间间隔内向所述反应室供应包含氮气的添加剂气体 第五个时间间隔。

    Methods of forming devices including different gate insulating layers on PMOS/NMOS regions
    3.
    发明授权
    Methods of forming devices including different gate insulating layers on PMOS/NMOS regions 有权
    在PMOS / NMOS区域上形成包括不同栅极绝缘层的器件的方法

    公开(公告)号：US07910421B2

    公开(公告)日：2011-03-22

    申请号：US12130646

    申请日：2008-05-30

    申请人： Sang-jin Hyun ,  Si-young Choi ,  In-sang Jeom ,  Gab-jin Nam ,  Sang-bom Kang ,  Sug-hun Hong

    发明人： Sang-jin Hyun ,  Si-young Choi ,  In-sang Jeom ,  Gab-jin Nam ,  Sang-bom Kang ,  Sug-hun Hong

    IPC分类号： H01L29/66

    CPC分类号： H01L21/823857 ,  H01L21/28202 ,  H01L21/31155 ,  H01L29/513 ,  H01L29/518

    摘要： Provided is a method of manufacturing a semiconductor device, in which the thickness of a gate insulating layer of a CMOS device can be controlled. The method can include selectively injecting fluorine (F) into a first region on a substrate and avoiding injecting the fluorine (F) into a second region on the substrate. A first gate insulating layer is formed of oxynitride layers on the first and second regions to have first and second thicknesses, respectively, where the first thickness is less than the second thickness. A second gate insulating layer is formed on the first gate insulating layer and a gate electrode pattern is formed on the second gate insulating layer.

    摘要翻译： 提供一种制造半导体器件的方法，其中可以控制CMOS器件的栅极绝缘层的厚度。 该方法可以包括将氟（F）选择性地注入到衬底上的第一区域中，并且避免将氟（F）注入到衬底上的第二区域中。 第一栅极绝缘层由第一和第二区域上的氧氮化物层形成，以分别具有第一和第二厚度，其中第一厚度小于第二厚度。 在第一栅极绝缘层上形成第二栅极绝缘层，并且在第二栅极绝缘层上形成栅电极图案。

    Method for forming metal layer of semiconductor device using metal halide gas
    4.
    发明授权
    Method for forming metal layer of semiconductor device using metal halide gas 有权
    使用金属卤化物气体形成半导体器件的金属层的方法

    公开(公告)号：US06458701B1

    公开(公告)日：2002-10-01

    申请号：US09686622

    申请日：2000-10-12

    申请人： Yun-sook Chae ,  Sang-bom Kang ,  Gil-heyun Choi ,  In-sang Jeon

    发明人： Yun-sook Chae ,  Sang-bom Kang ,  Gil-heyun Choi ,  In-sang Jeon

    IPC分类号： C23L1608

    CPC分类号： C23C16/0281 ,  C23C16/0218 ,  C23C16/14 ,  H01L21/28556 ,  H01L21/28568

    摘要： A method for forming a metal layer located over a metal underlayer of a semiconductor device, using a metal halogen gas. The method involves supplying a predetermined reaction gas into a reaction chamber for a predetermined period of time prior to deposition of the metal layer. The reaction gas has a higher reactivity with an active halogen element of a metal halogen gas supplied to form the metal layer, compared to a metal element of the metal halogen gas. As the metal halogen gas is supplied into the reaction chamber, the reaction gas reacts with the halogen radicals of the metal halogen gas, so that the metal underlayer is protected from being contaminated by impurities containing the halogen radicals.

    摘要翻译： 一种使用金属卤素气体形成位于半导体器件的金属底层上的金属层的方法。 该方法包括在沉积金属层之前将预定的反应气体提供给反应室预定的时间。 与金属卤素气体的金属元素相比，反应气体与供给的金属卤素气体的活性卤素元素的反应性较高，形成金属层。 当将金属卤素气体供应到反应室中时，反应气体与金属卤素气体的卤素自由基反应，从而保护金属底层免受含有卤素基团的杂质的污染。

    METHODS OF FORMING DEVICES INCLUDING DIFFERENT GATE INSULATING LAYERS ON PMOS/NMOS REGIONS
    5.
    发明申请
    METHODS OF FORMING DEVICES INCLUDING DIFFERENT GATE INSULATING LAYERS ON PMOS/NMOS REGIONS 有权
    在PMOS / NMOS区域形成不同栅绝缘层的器件的方法

    公开(公告)号：US20080305620A1

    公开(公告)日：2008-12-11

    申请号：US12130646

    申请日：2008-05-30

    申请人： Sang-jin Hyun ,  Si-young Choi ,  In-sang Jeom ,  Gab-jin Nam ,  Sang-bom Kang ,  Sug-hun Hong

    发明人： Sang-jin Hyun ,  Si-young Choi ,  In-sang Jeom ,  Gab-jin Nam ,  Sang-bom Kang ,  Sug-hun Hong

    IPC分类号： H01L21/425

    CPC分类号： H01L21/823857 ,  H01L21/28202 ,  H01L21/31155 ,  H01L29/513 ,  H01L29/518

    摘要： Provided is a method of manufacturing a semiconductor device, in which the thickness of a gate insulating layer of a CMOS device can be controlled. The method can include selectively injecting fluorine (F) into a first region on a substrate and avoiding injecting the fluorine (F) into a second region on the substrate. A first gate insulating layer is formed of oxynitride layers on the first and second regions to have first and second thicknesses, respectively, where the first thickness is less than the second thickness. A second gate insulating layer is formed on the first gate insulating layer and a gate electrode pattern is formed on the second gate insulating layer.

    摘要翻译： 提供一种制造半导体器件的方法，其中可以控制CMOS器件的栅极绝缘层的厚度。 该方法可以包括将氟（F）选择性地注入到衬底上的第一区域中，并且避免将氟（F）注入到衬底上的第二区域中。 第一栅极绝缘层由第一和第二区域上的氧氮化物层形成，以分别具有第一和第二厚度，其中第一厚度小于第二厚度。 在第一栅极绝缘层上形成第二栅极绝缘层，并且在第二栅极绝缘层上形成栅电极图案。

    Semiconductor Devices Having Transistors with Different Gate Structures and Related Methods
    6.
    发明申请
    Semiconductor Devices Having Transistors with Different Gate Structures and Related Methods 审中-公开
    具有不同栅极结构的晶体管的半导体器件及相关方法

    公开(公告)号：US20080116530A1

    公开(公告)日：2008-05-22

    申请号：US11855413

    申请日：2007-09-14

    申请人： Sang-jin Hyun ,  Si-young Choi ,  In-sang Jeon ,  Sang-bom Kang ,  Hye-min Kim

    发明人： Sang-jin Hyun ,  Si-young Choi ,  In-sang Jeon ,  Sang-bom Kang ,  Hye-min Kim

    IPC分类号： H01L29/94 ,  H01L21/8238

    CPC分类号： H01L21/823828 ,  H01L21/823437 ,  H01L21/82345 ,  H01L21/823462 ,  H01L21/823842 ,  H01L21/823857 ,  H01L27/10873 ,  H01L27/10876 ,  H01L27/10894 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66621

    摘要： A semiconductor device may include a semiconductor substrate and first and second transistors. The first transistor may have a first gate structure on the semiconductor substrate, and the first gate structure may include a first gate insulating layer between a first gate electrode and the semiconductor substrate. The first gate insulating layer may include first and second dielectric materials with the second dielectric material having a greater dielectric constant than the first dielectric material. Moreover, the first gate electrode may be in contact with the second dielectric material. The second transistor may have a second gate structure on the semiconductor substrate, with the second gate structure including a second gate insulating layer between a second gate electrode and the semiconductor substrate. Related methods are also discussed.

    摘要翻译： 半导体器件可以包括半导体衬底和第一和第二晶体管。 第一晶体管可以在半导体衬底上具有第一栅极结构，并且第一栅极结构可以包括在第一栅极电极和半导体衬底之间的第一栅极绝缘层。 第一栅极绝缘层可以包括第一和第二介电材料，其中第二介电材料具有比第一介电材料更大的介电常数。 此外，第一栅电极可以与第二电介质材料接触。 第二晶体管可以在半导体衬底上具有第二栅极结构，其中第二栅极结构包括在第二栅电极和半导体衬底之间的第二栅极绝缘层。 还讨论了相关方法。

    Methods of forming metal wiring in semiconductor devices using etch stop layers
    8.
    发明授权
    Methods of forming metal wiring in semiconductor devices using etch stop layers 有权
    使用蚀刻停止层在半导体器件中形成金属布线的方法

    公开(公告)号：US07521357B2

    公开(公告)日：2009-04-21

    申请号：US11063936

    申请日：2005-02-23

    申请人： Sang-woo Lee ,  Gil-heyun Choi ,  Sang-bom Kang ,  Jong-myeong Lee ,  Jin-ho Park

    发明人： Sang-woo Lee ,  Gil-heyun Choi ,  Sang-bom Kang ,  Jong-myeong Lee ,  Jin-ho Park

    IPC分类号： H01L21/4763

    CPC分类号： H01L21/76846 ,  H01L21/76841 ,  H01L21/76856 ,  H01L21/76877

    摘要： A method of forming a metal wiring in a semiconductor device can include forming an etch stop layer outside a contact hole formed in an insulation layer and avoiding forming the etch stop layer inside the contact hole. A conductive layer can be formed on the etch stop layer outside the contact hole and on an exposed conductive pattern inside the contact hole and on a sidewall of the contact hole and a metal layer can be formed on the conductive layer to fill the contact hole.

    摘要翻译： 在半导体器件中形成金属布线的方法可以包括在形成在绝缘层中的接触孔之外形成蚀刻停止层，并避免在接触孔内形成蚀刻停止层。 可以在接触孔外部的蚀刻停止层上形成导电层，并且在接触孔内部和接触孔的侧壁上的暴露的导电图案上形成导电层，并且可以在导电层上形成金属层以填充接触孔。

    Method of forming cobalt disilicide layer and method of manufacturing semiconductor device using the same
    10.
    发明申请
    Method of forming cobalt disilicide layer and method of manufacturing semiconductor device using the same 有权
    形成二硅化钴层的方法和使用其制造半导体器件的方法

    公开(公告)号：US20050136659A1

    公开(公告)日：2005-06-23

    申请号：US10936853

    申请日：2004-09-09

    申请人： Jong-ho Yun ,  Gil-heyun Choi ,  Sang-bom Kang ,  Woong-hee Sohn ,  Hyun-su Kim

    发明人： Jong-ho Yun ,  Gil-heyun Choi ,  Sang-bom Kang ,  Woong-hee Sohn ,  Hyun-su Kim

    IPC分类号： H01L21/24 ,  H01L21/285 ,  H01L21/324 ,  H01L21/336 ,  H01L21/44 ,  H01L21/4763 ,  H01L21/768 ,  H01L29/78

    CPC分类号： H01L21/324 ,  H01L21/28518 ,  H01L21/28556 ,  H01L21/76889 ,  H01L29/665 ,  H01L29/78

    摘要： A method of forming a cobalt disilicide layer and a method of manufacturing a semiconductor device using the same are provided. The method of forming a cobalt disilicide layer includes forming a cobalt layer on at least a silicon surface of a semiconductor device using metal organic chemical vapor deposition by supplying a cobalt precursor having a formula Co2(CO)6(R1—C≡C—R2), where R1 is H or CH3, and R2 is hydrogen, t-butyl, phenyl, methyl, or ethyl, as a source gas. Then, a capping layer is formed on the cobalt layer. A first thermal treatment is then performed on the semiconductor device in an ultra high vacuum, for example, under a pressure of 10−9-10−3 torr, to react silicon with cobalt. Cobalt unreacted during the first thermal treatment and the capping layer are then removed and a second thermal treatment is performed on the semiconductor device to form the cobalt disilicide (CoSi2) layer.

    摘要翻译： 提供了形成二硅化钴层的方法以及使用其制造半导体器件的方法。 形成二硅化钴层的方法包括使用金属有机化学气相沉积在半导体器件的至少硅表面上形成钴层，通过提供具有式CO 2（CO）2的钴前体， （R 1-C≡CR2），其中R 1是H或CH 3， / SUB，R 2是作为源气体的氢，叔丁基，苯基，甲基或乙基。 然后，在钴层上形成覆盖层。 然后在超高真空下，例如在10 -9 -10 -3托的压力下，在半导体器件上进行第一热处理，以使硅 与钴。 然后去除在第一热处理期间未反应的钴和覆盖层，并在半导体器件上进行第二热处理以形成二硅化钴（CoSi 2 N 2）层。