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    Semiconductor memory of good retention and its manufacture
    1.
    发明授权
    Semiconductor memory of good retention and its manufacture 有权
    半导体存储器具有良好的保留和制造

    公开(公告)号：US06706580B2

    公开(公告)日：2004-03-16

    申请号：US09935749

    申请日：2001-08-24

    申请人： Taiji Ema ,  Koichi Hashimoto

    发明人： Taiji Ema ,  Koichi Hashimoto

    IPC分类号： H01L218238

    CPC分类号： H01L27/10855 ,  H01L27/10891

    摘要： A plurality of memory cell transistors are formed on a principal surface of a semiconductor substrate in a plurality of active regions defined by an isolation region. Each memory cell transistor uses one word line as its gate electrode and has a pair of source and drain regions defined by the gate electrode and the isolation region. One of a pair of source and drain regions is connected to one of a plurality of bit lines, and the other region is connected to one of a plurality of capacitors. Three sides of the other region are defined by the isolation region. The other region includes a first impurity doped region extending to under another word line adjacent to the one word line and a second impurity doped region partially overlapping the first impurity doped region and the gate electrode.

    摘要翻译： 在由隔离区域限定的多个有源区域中的半导体衬底的主表面上形成多个存储单元晶体管。 每个存储单元晶体管使用一个字线作为其栅极，并且具有由栅电极和隔离区限定的一对源极和漏极区。 一对源极和漏极区域中的一个连接到多个位线之一，另一个区域连接到多个电容器中的一个。 另一区域的三面由隔离区限定。 另一区域包括延伸到与一条字线相邻的另一字线下方的第一杂质掺杂区域和部分地与第一杂质掺杂区域和栅电极重叠的第二杂质掺杂区域。

    Semiconductor memory of good retention and its manufacture
    2.
    发明授权
    Semiconductor memory of good retention and its manufacture 有权
    半导体存储器具有良好的保留和制造

    公开(公告)号：US06300655B1

    公开(公告)日：2001-10-09

    申请号：US09265400

    申请日：1999-03-10

    申请人： Taiji Ema ,  Koichi Hashimoto

    发明人： Taiji Ema ,  Koichi Hashimoto

    IPC分类号： H01L27108

    CPC分类号： H01L27/10855 ,  H01L27/10891

    摘要： A plurality of memory cell transistors are formed on a principal surface of a semiconductor substrate in a plurality of active regions defined by an isolation region. Each memory cell transistor uses one word line as its gate electrode and has a pair of source and drain regions defined by the gate electrode and the isolation region. One of a pair of source and drain regions is connected to one of a plurality of bit lines, and the other region is connected to one of a plurality of capacitors. Three sides of the other region are defined by the isolation region. The other region includes a first impurity doped region extending to under another word line adjacent to the one word line and a second impurity doped region partially overlapping the first impurity doped region and the gate electrode.

    摘要翻译： 在由隔离区域限定的多个有源区域中的半导体衬底的主表面上形成多个存储单元晶体管。 每个存储单元晶体管使用一个字线作为其栅极，并且具有由栅电极和隔离区限定的一对源极和漏极区。 一对源极和漏极区域中的一个连接到多个位线之一，另一个区域连接到多个电容器中的一个。 另一区域的三面由隔离区限定。 另一区域包括延伸到与一条字线相邻的另一字线下方的第一杂质掺杂区域和部分地与第一杂质掺杂区域和栅电极重叠的第二杂质掺杂区域。

    Semiconductor memory device with bit line contact areas and storage capacitor contact areas
    3.
    发明授权
    Semiconductor memory device with bit line contact areas and storage capacitor contact areas 失效

    公开(公告)号：US5812444A

    公开(公告)日：1998-09-22

    申请号：US669765

    申请日：1996-06-25

    申请人： Taiji Ema ,  Koichi Hashimoto

    发明人： Taiji Ema ,  Koichi Hashimoto

    IPC分类号： G11C11/401 ,  H01L21/8242 ,  H01L27/10 ,  H01L27/108 ,  G11C11/24

    CPC分类号： H01L27/10808 ,  H01L27/10805

    摘要： A semiconductor memory device includes a plurality of memory cells located at intersections of the word lines and the bit lines, each of the memory cells having a capacitor for storing information and a transfer transistor for reading information from and writing information into the capacitor, the gate of the transfer transistor being connected to a word line, the source of the transfer transistor being connected through a bit line contact area to a bit line, the drain of said transfer transistor being connected through a storage capacitor contact area to the storage electrode of the capacitor. A memory cell pair is formed by two nearby memory cells and these two memory cells of the memory cell pair have a common bit line contact area. In a unit region defined by word line Nos. "i" and "i+1" and bit line Nos. "j" and "j+4", there are provided bit line contact areas and storage capacitor contact areas with a ratio of 1:2 between the number of the bit line contact areas and the storage capacitor contact areas.

    Semiconductor memory device with bit line contact areas and storage capacitor contact areas
    4.
    发明授权
    Semiconductor memory device with bit line contact areas and storage capacitor contact areas 失效
    半导体存储器件具有位线接触区域和存储电容接触区域

    公开(公告)号：US6026010A

    公开(公告)日：2000-02-15

    申请号：US93821

    申请日：1998-06-09

    申请人： Taiji Ema ,  Koichi Hashimoto

    发明人： Taiji Ema ,  Koichi Hashimoto

    IPC分类号： G11C11/401 ,  H01L21/8242 ,  H01L27/10 ,  H01L27/108 ,  G11C11/24

    CPC分类号： H01L27/10808 ,  H01L27/10805

    摘要： A semiconductor memory device includes a plurality of memory cells located at intersections of the word lines and the bit lines, each of the memory cells having a capacitor for storing information and a transfer transistor for reading information from and writing information into the capacitor, the gate of the transfer transistor being connected to a word line, the source of the transfer transistor being connected through a bit line contact area to a bit line, the drain of said transfer transistor being connected through a storage capacitor contact area to the storage electrode of the capacitor. A memory cell pair is formed by two nearby memory cells and these two memory cells of the memory cell pair have a common bit line contact area. In a unit region defined by word line Nos. "i" and "i+1" and bit line Nos. "j" and "j+4", there are provided bit line contact areas and storage capacitor contact areas with a ratio of 1:2 between the number of the bit line contact areas and the storage capacitor contact areas.

    摘要翻译： 半导体存储器件包括位于字线和位线的交点处的多个存储器单元，每个存储单元具有用于存储信息的电容器和用于从信息读取信息并将信息写入电容器的转移晶体管，栅极 所述传输晶体管的源极连接到字线，所述传输晶体管的源极通过位线接触区域连接到位线，所述传输晶体管的漏极通过存储电容器接触区域连接到所述存储电极 电容器。 存储单元对由两个附近的存储器单元形成，并且存储单元对的这两个存储单元具有公共位线接触区域。 在由字线号“i”和“i + 1”以及位线号“j”和“j + 4”定义的单位区域中，提供了位线接触区域和存储电容器接触区域，比例为 1：2之间的位线接触面积数量与存储电容接触面积之间。

    Semiconductor device, semiconductor wafer and manufacturing method of semiconductor device
    5.
    发明授权
    Semiconductor device, semiconductor wafer and manufacturing method of semiconductor device 有权

    公开(公告)号：US08921981B2

    公开(公告)日：2014-12-30

    申请号：US13618389

    申请日：2012-09-14

    申请人： Kazutaka Yoshizawa ,  Taiji Ema ,  Takuya Moriki

    发明人： Kazutaka Yoshizawa ,  Taiji Ema ,  Takuya Moriki

    IPC分类号： H01L23/544 ,  H01L21/78 ,  H01L21/66

    摘要： A semiconductor device includes wiring layers formed over a semiconductor wafer, a via-layer between the wiring layers, conductive films in the wiring layers, and a via-plug in the via-layer connecting the conductive films of the wiring layers above and below, a scribe region at an outer periphery of a chip region along an edge of the semiconductor substrate and including a pad region in the vicinity of the edge, the pad region overlapping the conductive films of the plurality of wiring layers in the plan view, the plurality of wiring layers including first second wiring layers, the conductive film of the first wiring layer includes a first conductive pattern formed over an entire surface of said pad region in a plan view, and the conductive film of the second wiring layer includes a second conductive pattern formed in a part of the pad region in a plan view.

    Semiconductor device and method of manufacturing the same
    7.
    发明授权
    Semiconductor device and method of manufacturing the same 有权
    半导体装置及其制造方法

    公开(公告)号：US08283729B2

    公开(公告)日：2012-10-09

    申请号：US13010255

    申请日：2011-01-20

    申请人： Tomohiko Tsutsumi ,  Taiji Ema ,  Hideyuki Kojima ,  Toru Anezaki

    发明人： Tomohiko Tsutsumi ,  Taiji Ema ,  Hideyuki Kojima ,  Toru Anezaki

    IPC分类号： H01L23/62

    CPC分类号： H01L27/0629 ,  H01L21/823814 ,  H01L21/823857 ,  H01L27/0266 ,  H01L27/105 ,  H01L27/11526 ,  H01L27/11546

    摘要： The semiconductor device includes a first MIS transistor including a gate insulating film 92, a gate electrode 108 formed on the gate insulating film 92 and source/drain regions 154, a second MIS transistor including a gate insulating film 96 thicker than the gate insulating film 92, a gate electrode 108 formed on the gate insulating film 96, source/drain regions 154 and a ballast resistor 120 connected to one of the source/drain regions 154, a salicide block insulating film 146 formed on the ballast resistor 120 with an insulating film 92 thinner than the gate insulating film 96 interposed therebetween, and a silicide film 156 formed on the source/drain regions 154.

    摘要翻译： 半导体器件包括第一MIS晶体管，其包括栅极绝缘膜92，形成在栅极绝缘膜92和源极/漏极区154上的栅电极108，包括比栅极绝缘膜92厚的栅极绝缘膜96的第二MIS晶体管 形成在栅极绝缘膜96上的栅极电极108，源极/漏极区域154以及连接到源极/漏极区域154之一的镇流电阻器120，在具有绝缘膜的镇流电阻器120上形成的自对准硅绝缘膜146 92，比其间的栅极绝缘膜96薄，以及形成在源极/漏极区154上的硅化物膜156。

    SEMICONDUCTOR DEVICE
    8.
    发明申请
    SEMICONDUCTOR DEVICE 失效
    半导体器件

    公开(公告)号：US20100283092A1

    公开(公告)日：2010-11-11

    申请号：US12839867

    申请日：2010-07-20

    申请人： Taiji Ema ,  Tohru Anezaki

    发明人： Taiji Ema ,  Tohru Anezaki

    IPC分类号： H01L27/108

    CPC分类号： H01L27/10852 ,  H01L21/76897 ,  H01L27/105 ,  H01L27/10873 ,  H01L27/10894 ,  H01L27/10897

    摘要： The semiconductor device includes a first conductor formed over a semiconductor substrate; a first insulator formed over the first conductor; a second insulator formed over the first insulator, the second insulator having an etching characteristic different from an etching characteristic of the first insulator; a second conductor formed on the second insulator, the second conductor being in contact with the second insulator; a third insulator formed over the second conductor, the third insulator having an etching characteristic different from the etching characteristic of the second insulator; a first contact hole formed through the third insulator and the second conductor, the first contact hole reaching the second insulator; a third conductor formed in the first contact hole, wherein a side wall of the third conductor is electrically connected to a side wall of the second conductor; a second contact hole formed through the third insulator and the first insulator, the second contact hole reaching the first conductor; and a fourth conductor formed in the second contact hole, wherein the fourth conductor is electrically connected to the first conductor.

    摘要翻译： 半导体器件包括形成在半导体衬底上的第一导体; 形成在所述第一导体上的第一绝缘体; 形成在所述第一绝缘体上的第二绝缘体，所述第二绝缘体具有与所述第一绝缘体的蚀刻特性不同的蚀刻特性; 形成在所述第二绝缘体上的第二导体，所述第二导体与所述第二绝缘体接触; 形成在所述第二导体上的第三绝缘体，所述第三绝缘体具有与所述第二绝缘体的蚀刻特性不同的蚀刻特性; 通过第三绝缘体和第二导体形成的第一接触孔，第一接触孔到达第二绝缘体; 形成在第一接触孔中的第三导体，其中第三导体的侧壁电连接到第二导体的侧壁; 形成为穿过所述第三绝缘体和所述第一绝缘体的第二接触孔，所述第二接触孔到达所述第一导体; 以及形成在所述第二接触孔中的第四导体，其中所述第四导体电连接到所述第一导体。

    SEMICONDUCTOR MEMORY DEVICE AND SEMICONDUCTOR DEVICE GROUP
    9.
    发明申请
    SEMICONDUCTOR MEMORY DEVICE AND SEMICONDUCTOR DEVICE GROUP 有权
    半导体存储器件和半导体器件组

    公开(公告)号：US20100238716A1

    公开(公告)日：2010-09-23

    申请号：US12792115

    申请日：2010-06-02

    申请人： Toru Anezaki ,  Tomohiko Tsutsumi ,  Tatsuji Araya ,  Hideyuki Kojima ,  Taiji Ema

    发明人： Toru Anezaki ,  Tomohiko Tsutsumi ,  Tatsuji Araya ,  Hideyuki Kojima ,  Taiji Ema

    IPC分类号： G11C11/00 ,  G11C11/34

    CPC分类号： H01L27/1104 ,  G11C5/063 ,  G11C11/412 ,  H01L27/11 ,  Y10S257/903

    摘要： A semiconductor device includes a first CMOS inverter, a second CMOS inverter, a first transfer transistor and a second transfer transistor wherein the first and second transfer transistors are formed respectively in first and second device regions defined on a semiconductor device by a device isolation region so as to extend in parallel with each other, the first transfer transistor contacting with a first bit line at a first bit contact region on the first device region, the second transfer transistor contacting with a second bit line at a second bit contact region on the second device region, wherein the first bit contact region is formed in the first device region such that a center of said the bit contact region is offset toward the second device region, and wherein the second bit contact region is formed in the second device region such that a center of the second bit contact region is offset toward the first device region.

    摘要翻译： 半导体器件包括第一CMOS反相器，第二CMOS反相器，第一传输晶体管和第二传输晶体管，其中第一和第二传输晶体管分别形成在由器件隔离区限定在半导体器件上的第一和第二器件区域中， 为了彼此并联延伸，第一传输晶体管在第一器件区域上的第一位接触区域处与第一位线接触，第二传输晶体管在第二位线处与第二位线接触，第二位线在第二位接触区域处 器件区域，其中第一位接触区域形成在第一器件区域中，使得所述位接触区域的中心朝向第二器件区域偏移，并且其中第二位接触区域形成在第二器件区域中，使得 第二位接触区域的中心朝向第一器件区域偏移。