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    Method of treating semiconductor substrate
    1.
    发明授权
    Method of treating semiconductor substrate 有权

    公开(公告)号：US11127583B2

    公开(公告)日：2021-09-21

    申请号：US16542036

    申请日：2019-08-15

    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

    Inventor： Chung-Hao Chang ,  Chitong Chen

    IPC: H01L21/02 ,  H01L21/027 ,  C23C16/455 ,  B05D1/00

    Abstract: A method of treating a semiconductor substrate includes converting a first main side of the semiconductor substrate having a first coefficient of static friction relative to a surface of a wafer table to a second coefficient of static friction relative to the surface of the wafer table, wherein the second coefficient of static friction is less than the first coefficient of static friction. A photoresist layer is applied over a second main side of the semiconductor substrate having the first coefficient of static friction. The second main side opposes the first main side. The semiconductor substrate is placed on the wafer table so that the first main side of the semiconductor substrate faces the wafer table.

    Tool And Method Of Developing
    2.
    发明申请
    Tool And Method Of Developing 有权
    工具和开发方法

    公开(公告)号：US20150241786A1

    公开(公告)日：2015-08-27

    申请号：US14189169

    申请日：2014-02-25

    Applicant: Taiwan Semiconductor Manufacturing CO., LTD.

    Inventor： Yi-Rem Chen ,  Ming-Shane Lu ,  Chung-Hao Chang ,  Jui-Ping Chuang ,  Li-Kong Turn ,  Fei-Gwo Tsai

    IPC: G03F7/30

    CPC classification number: G03F7/3021 ,  H01L21/67051 ,  H01L21/6715

    Abstract: A tool and a method of developing are provided. In various embodiments, the method of developing includes rotating a wafer at a first rotating speed. The method further includes dispensing a developer solution onto the wafer at the first rotating speed by a first nozzle above the wafer, wherein the first nozzle moves back and forth along a path during dispensing the developer solution. The method further includes rotating the wafer at a second rotating speed to spread the developer solution onto the wafer uniformly. The method further includes dispensing a rinse solution onto the wafer at the second rotating speed by a second nozzle above the wafer.

    Abstract translation: 提供了一种工具和开发方法。 在各种实施例中，显影方法包括以第一旋转速度旋转晶片。 该方法还包括通过晶片上方的第一喷嘴以第一转速将显影剂溶液分配到晶片上，其中在分配显影剂溶液期间第一喷嘴沿着路径前后移动。 该方法还包括以第二转速旋转晶片以将显影剂溶液均匀地分散在晶片上。 该方法还包括通过晶片上方的第二喷嘴以第二转速将冲洗溶液分配到晶片上。

    Developing method
    4.
    发明授权
    Developing method 有权

    公开(公告)号：US11150558B2

    公开(公告)日：2021-10-19

    申请号：US16849818

    申请日：2020-04-15

    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

    Inventor： Yi-Rem Chen ,  Ming-Shane Lu ,  Chung-Hao Chang ,  Jui-Ping Chuang ,  Li-Kong Turn ,  Fei-Gwo Tsai

    IPC: G03F7/30 ,  H01L21/67

    Abstract: A developing method is provided. The developing method includes rotating a wafer. The developing method also includes dispensing, through a first nozzle, a developer solution onto the rotated wafer through a first nozzle at a first rotating speed. The developing method further includes dispensing, through a second nozzle, a rinse solution onto the rotated wafer through a second nozzle at a second rotating speed. The second rotating speed is less than the first rotating speed. In addition, the developing method includes simultaneously moving the first nozzle and the second nozzle during either the dispensing of the developer solution or the dispensing of the rinse solution.

    Developing method
    5.
    发明授权
    Developing method 有权

    公开(公告)号：US10101662B2

    公开(公告)日：2018-10-16

    申请号：US15676925

    申请日：2017-08-14

    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

    Inventor： Yi-Rem Chen ,  Ming-Shane Lu ,  Chung-Hao Chang ,  Jui-Ping Chuang ,  Li-Kong Turn ,  Fei-Gwo Tsai

    IPC: B08B3/08 ,  G03F7/30 ,  H01L21/67

    Abstract: A developing method includes rotating a wafer. A developer solution is dispensed onto the rotated wafer through a first nozzle. The first nozzle is moved from a first position to a second position. The first position and the second position are over the wafer and within a perimeter of the wafer when viewed from a top of the wafer. The developer solution is dispensed through the first nozzle when moving the first nozzle from the first position to the second position. The first nozzle is moved back from the second position to the first position immediately after the first nozzle is moved from the first position to the second position. The developer solution is dispensed through the first nozzle when moving the first nozzle from the second position to the first position.

    Overlay sampling methodology
    6.
    发明授权
    Overlay sampling methodology 有权
    覆盖抽样方法

    公开(公告)号：US09442391B2

    公开(公告)日：2016-09-13

    申请号：US13942810

    申请日：2013-07-16

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Han-Ming Hsieh ,  Li-Shiuan Chen ,  Chung-Hao Chang ,  Li-Kong Turn

    IPC: H01L21/68 ,  G01B11/14 ,  G06F17/40 ,  G06F19/00 ,  G03F7/20

    CPC classification number: G03F7/70633 ,  G01B11/14 ,  G06F17/40 ,  G06F19/00 ,  H01L21/68

    Abstract: One embodiment relates to a method to achieve enhanced overlay control while maintaining manufacturing throughput for a fabrication process. Locations of a plurality of alignment structures on a wafer comprising a plurality of reticle fields are determined with a layout tool to define a layout-based wafer map. The topography of the wafer is then measured as a function of wafer position by a surface measuring tool. The layout-based wafer map is then projected onto the measured wafer topography to define a modeled wafer map. A subset of alignment structure locations are measured with an alignment tool in an in-line fabrication flow so as not to delay subsequent fabrication steps. Disagreement between the measured alignment structure locations and modeled alignment structure locations is then minimized mathematically to enhance overlay control while maintaining manufacturing throughput.

    Abstract translation: 一个实施例涉及一种在维持制造过程的制造吞吐量的同时实现增强的覆盖控制的方法。 使用布局工具确定包括多个标线场的晶片上的多个对准结构的位置，以定义基于布局的晶片图。 然后通过表面测量工具作为晶片位置的函数测量晶片的形貌。 然后将基于布局的晶片图投影到所测量的晶片形貌上以定义建模的晶片图。 对准结构位置的子集用在线制造流程中的对准工具测量，以便不延迟后续制造步骤。 然后在测量的对准结构位置和建模的对准结构位置之间的不一致性被数学地最小化以增强重叠控制，同时保持制造吞吐量。

    Overlay Sampling Methodology
    7.
    发明申请
    Overlay Sampling Methodology 有权
    覆盖抽样方法

    公开(公告)号：US20140278213A1

    公开(公告)日：2014-09-18

    申请号：US13942810

    申请日：2013-07-16

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Han-Ming Hsieh ,  Li-Shiuan Chen ,  Chung-Hao Chang ,  Li-Kong Turn

    IPC: G01B11/14

    CPC classification number: G03F7/70633 ,  G01B11/14 ,  G06F17/40 ,  G06F19/00 ,  H01L21/68

    Abstract: One embodiment relates to a method to achieve enhanced overlay control while maintaining manufacturing throughput for a fabrication process. Locations of a plurality of alignment structures on a wafer comprising a plurality of reticle fields are determined with a layout tool to define a layout-based wafer map. The topography of the wafer is then measured as a function of wafer position by a surface measuring tool. The layout-based wafer map is then projected onto the measured wafer topography to define a modeled wafer map. A subset of alignment structure locations are measured with an alignment tool in an in-line fabrication flow so as not to delay subsequent fabrication steps. Disagreement between the measured alignment structure locations and modeled alignment structure locations is then minimized mathematically to enhance overlay control while maintaining manufacturing throughput.

    Abstract translation: 一个实施例涉及一种在维持制造过程的制造吞吐量的同时实现增强的覆盖控制的方法。 使用布局工具确定包括多个标线场的晶片上的多个对准结构的位置，以定义基于布局的晶片图。 然后通过表面测量工具作为晶片位置的函数测量晶片的形貌。 然后将基于布局的晶片图投影到所测量的晶片形貌上以定义建模的晶片图。 对准结构位置的子集用在线制造流程中的对准工具测量，以便不延迟后续制造步骤。 然后在测量的对准结构位置和建模的对准结构位置之间的不一致性被数学地最小化以增强重叠控制，同时保持制造吞吐量。

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