公开(公告)号：US12250824B2

公开(公告)日：2025-03-11

申请号：US18511461

申请日：2023-11-16

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chung-Liang Cheng ,  Huang-Lin Chao

IPC: H01L29/423 ,  H01L23/522 ,  H01L23/528 ,  H10B51/10 ,  H10B51/20 ,  H10B53/00 ,  H10B53/10 ,  H10B53/20

Abstract: A ferroelectric memory cell (FeRAM) is disclosed that includes an active device (e.g., a transistor) and a passive device (e.g., a ferroelectric capacitor) integrated in a substrate. The transistor and its gate contacts are formed on a front side of the substrate. A carrier wafer can be bonded to the active device to allow the active device to be inverted so that the passive device and associated contacts can be electrically coupled from a back side of the substrate.

公开(公告)号：US12176392B2

公开(公告)日：2024-12-24

申请号：US17193547

申请日：2021-03-05

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chung-Liang Cheng

IPC: H01L27/088 ,  H01L21/8234 ,  H01L29/06 ,  H01L29/423 ,  H01L29/49 ,  H01L29/775 ,  H01L29/786 ,  H01L29/66

Abstract: A semiconductor process system etches gate metals on semiconductor wafers. The semiconductor process system includes a machine learning based analysis model. The analysis model dynamically selects process conditions for an atomic layer etching process. The process system then uses the selected process conditions data for the next etching process.

公开(公告)号：US20240371691A1

公开(公告)日：2024-11-07

申请号：US18774289

申请日：2024-07-16

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yen-Yu Chen ,  Chung-Liang Cheng

IPC: H01L21/768 ,  H01L21/225 ,  H01L21/311 ,  H01L29/40 ,  H01L29/417 ,  H01L29/45

Abstract: A method includes etching a dielectric layer to form a trench in the dielectric layer, depositing a metal layer extending into the trench, performing a nitridation process on the metal layer to convert a portion of the metal layer into a metal nitride layer, performing an oxidation process on the metal nitride layer to form a metal oxynitride layer, removing the metal oxynitride layer, and filling a metallic material into the trench using a bottom-up deposition process to form a contact plug.

公开(公告)号：US12002885B2

公开(公告)日：2024-06-04

申请号：US17470548

申请日：2021-09-09

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chung-Liang Cheng ,  Sheng-Tsung Wang ,  Huang-Lin Chao

IPC: H01L29/78 ,  B82Y10/00 ,  H01L21/285 ,  H01L21/768 ,  H01L21/8234 ,  H01L23/48 ,  H01L23/485 ,  H01L23/522 ,  H01L27/088 ,  H01L29/06 ,  H01L29/08 ,  H01L29/66 ,  H01L29/775

CPC classification number: H01L29/7851 ,  H01L21/823418 ,  H01L21/823431 ,  H01L23/481 ,  H01L29/0847 ,  H01L29/66795

Abstract: A semiconductor device and methods of fabricating the same are disclosed. The semiconductor device includes a substrate, a fin structure disposed on the substrate, a source/drain (S/D) region disposed on the fin structure, and a gate structure disposed on the fin structure adjacent to the S/D region. The gate structure includes a gate stack disposed on the fin structure and a gate capping structure disposed on the gate stack. The gate capping structure includes a conductive gate cap disposed on the gate stack and an insulating gate cap disposed on the conductive gate cap. The semiconductor device further includes a first contact structure disposed within the gate capping structure and a first via structure disposed on the first contact structure.

公开(公告)号：US11996328B2

公开(公告)日：2024-05-28

申请号：US17868654

申请日：2022-07-19

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chung-Liang Cheng ,  Ziwei Fang

IPC: H01L29/78 ,  H01L21/02 ,  H01L21/768 ,  H01L29/423

CPC classification number: H01L21/76877 ,  H01L21/02153 ,  H01L21/0217 ,  H01L21/0228 ,  H01L21/76816 ,  H01L21/76873

Abstract: A method for forming a gate structure includes forming a trench within an interlayer dielectric layer (ILD) that is disposed on a semiconductor substrate, the trench exposing a top surface of the semiconductor substrate, forming an interfacial layer at a bottom of the trench, forming a dielectric layer within the trench, forming a work function metal layer on the dielectric layer, forming an in-situ nitride layer on the work function metal layer in the trench, performing a first cobalt deposition process to form a cobalt layer within the trench, performing a second cobalt deposition process to increase a thickness of the cobalt layer within the trench, and performing an electrochemical plating (ECP) process to fill the trench with cobalt.

公开(公告)号：US11901242B2

公开(公告)日：2024-02-13

申请号：US17397186

申请日：2021-08-09

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chung-Liang Cheng ,  Ziwei Fang

IPC: H01L21/8238 ,  H01L29/06 ,  H01L29/10 ,  H01L29/08 ,  H01L29/423 ,  H01L27/092 ,  H01L21/28 ,  H01L21/285 ,  H01L21/3213 ,  H01L29/49

CPC classification number: H01L21/823842 ,  H01L21/28088 ,  H01L21/28556 ,  H01L21/32133 ,  H01L21/32139 ,  H01L21/823807 ,  H01L21/823821 ,  H01L27/0924 ,  H01L29/0673 ,  H01L29/0847 ,  H01L29/1037 ,  H01L29/42392 ,  H01L29/4966

Abstract: The structure of a semiconductor device with different gate structures configured to provide ultra-low threshold voltages and a method of fabricating the semiconductor device are disclosed. The semiconductor device includes first and second nanostructured channel regions in first and second nanostructured layers, respectively, and first and second gate-all-around (GAA) structures surrounding the first and second nanostructured channel regions, respectively. The first GAA structure includes an Al-based gate stack with a first gate dielectric layer, an Al-based n-type work function metal layer, a first metal capping layer, and a first gate metal fill layer. The second GAA structure includes an Al-free gate stack with a second gate dielectric layer, an Al-free p-type work function metal layer, a metal growth inhibition layer, a second metal capping layer, and a second gate metal fill layer.

公开(公告)号：US11532510B2

公开(公告)日：2022-12-20

申请号：US17176052

申请日：2021-02-15

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chung-Liang Cheng ,  Ziwei Fang

IPC: H01L23/532 ,  H01L23/522 ,  H01L21/768 ,  H01L29/78

Abstract: A semiconductor structure includes a metal gate structure disposed over a semiconductor substrate, an interlayer dielectric (ILD) layer disposed over the metal gate structure, and a gate contact disposed in the ILD layer and over the metal gate structure, where a bottom surface of the gate contact is defined by a barrier layer disposed over the metal gate structure, where sidewall surfaces of the gate contact are defined by and directly in contact with the ILD layer, and where the barrier layer is free of nitrogen.

公开(公告)号：US20220320180A1

公开(公告)日：2022-10-06

申请号：US17217000

申请日：2021-03-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kuan-Liang Liu ,  Sheng-Chau Chen ,  Chung-Liang Cheng ,  Chia-Shiung Tsai ,  Yeong-Jyh Lin ,  Pinyen Lin ,  Huang-Lin Chao

IPC: H01L27/22 ,  H01L29/06 ,  H01L29/423 ,  H01L29/45 ,  H01L29/786 ,  H01L21/02 ,  H01L21/285 ,  H01L29/66

Abstract: In some embodiments, the present disclosure relates to an integrated chip that includes a first and second transistors arranged over a substrate. The first transistor includes first channel structures extending between first and second source/drain regions. A first gate electrode is arranged between the first channel structures, and a first protection layer is arranged over a topmost one of the first channel structures. The second transistor includes second channel structures extending between the second source/drain region and a third source/drain region. A second gate electrode is arranged between the second channel structures, and a second protection layer is arranged over a topmost one of the second channel structures. The integrated chip further includes a first interconnect structure arranged between the substrate and the first and second channel structures, and a contact plug structure coupled to the second source/drain region and arranged above the first and second gate electrodes.

公开(公告)号：US20220285225A1

公开(公告)日：2022-09-08

申请号：US17750579

申请日：2022-05-23

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chung-Liang Cheng ,  Ziwei Fang

IPC: H01L21/8238 ,  H01L27/092 ,  H01L29/66 ,  H01L29/78 ,  H01L21/02

Abstract: A method of manufacturing a semiconductor device is provided. A substrate is provided. The substrate has a first region and a second region. An n-type work function layer is formed over the substrate in the first region but not in the second region. A p-type work function layer is formed over the n-type work function layer in the first region, and over the substrate in the second region. The p-type work function layer directly contacts the substrate in the second region. And the p-type work function layer includes a metal oxide.

公开(公告)号：US11342231B2

公开(公告)日：2022-05-24

申请号：US16573866

申请日：2019-09-17

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chung-Liang Cheng ,  Ziwei Fang

IPC: H01L21/8238 ,  H01L27/092 ,  H01L29/66 ,  H01L29/78 ,  H01L21/02

Abstract: A method of manufacturing a semiconductor device is provided. A substrate is provided. The substrate has a first region and a second region. An n-type work function layer is formed over the substrate in the first region but not in the second region. A p-type work function layer is formed over the n-type work function layer in the first region, and over the substrate in the second region. The p-type work function layer directly contacts the substrate in the second region. And the p-type work function layer includes a metal oxide.