公开(公告)号：US11837312B1

公开(公告)日：2023-12-05

申请号：US17807967

申请日：2022-06-21

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chia-Hsiang Chen ,  Chih-Yang Chang ,  Chia Yu Wang ,  Meng-Chun Shih

IPC: G11C29/44 ,  G11C29/12 ,  G11C29/46

CPC classification number: G11C29/4401 ,  G11C29/12005 ,  G11C29/12015 ,  G11C29/46

Abstract: The present disclosure describes a magnetic memory device. The magnetic memory device includes a magnetic sensing array configured to sense an external magnetic field strength. The magnetic memory device further includes a voltage modulator configured to, in response to the external magnetic field strength being greater than a threshold magnetic field strength, provide a test voltage different from a current write voltage of the magnetic memory device. The magnetic memory device further includes an error check array configured to use the test voltage as a write voltage of the error check array and provide a bit error rate corresponding to the test voltage. The magnetic memory device further includes a control unit configured to adjust, based on the bit error rate being equal to or less than a threshold bit error rate, a write voltage of the magnetic memory device from the current write voltage to the test voltage.

公开(公告)号：US20210109152A1

公开(公告)日：2021-04-15

申请号：US17126222

申请日：2020-12-18

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Harry-Hak-Lay Chuang ,  Chih-Yang Chang ,  Ching-Huang Wang ,  Tien-Wei Chiang ,  Meng-Chun Shih ,  Chia Yu Wang

IPC: G01R31/28 ,  G01R1/16 ,  G11C11/16 ,  G11C29/56

Abstract: In some embodiments, a semiconductor wafer testing system is provided. The semiconductor wafer testing system includes a semiconductor wafer prober having one or more conductive probes, where the semiconductor wafer prober is configured to position the one or more conductive probes on an integrated chip (IC) that is disposed on a semiconductor wafer. The semiconductor wafer testing system also includes a ferromagnetic wafer chuck, where the ferromagnetic wafer chuck is configured to hold the semiconductor wafer while the wafer prober positions the one or more conductive probes on the IC. An upper magnet is disposed over the ferromagnetic wafer chuck, where the upper magnet is configured to generate an external magnetic field between the upper magnet and the ferromagnetic wafer chuck, and where the ferromagnetic wafer chuck amplifies the external magnetic field such that the external magnetic field passes through the IC with an amplified magnetic field strength.

公开(公告)号：US11531524B2

公开(公告)日：2022-12-20

申请号：US16434345

申请日：2019-06-07

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Harry-Hak-Lay Chuang ,  Chih-Yang Chang ,  Ching-Huang Wang ,  Chih-Hui Weng ,  Tien-Wei Chiang ,  Meng-Chun Shih ,  Chia Yu Wang ,  Chia-Hsiang Chen

IPC: G06F7/58 ,  G11C11/16

Abstract: In some embodiments, a method for generating a random bit is provided. The method includes generating a first random bit by providing a random number generator (RNG) signal to a magnetoresistive random-access memory (MRAM) cell. The RNG signal has a probability of about 0.5 to switch the resistive state of the MRAM cell from a first resistive state corresponding to a first data state to a second resistive state corresponding to a second data state. The first random bit is then read from the MRAM cell.

公开(公告)号：US11506706B2

公开(公告)日：2022-11-22

申请号：US17126222

申请日：2020-12-18

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Harry-Hak-Lay Chuang ,  Chih-Yang Chang ,  Ching-Huang Wang ,  Tien-Wei Chiang ,  Meng-Chun Shih ,  Chia Yu Wang

IPC: G01R31/26 ,  G01R31/28 ,  G11C11/16 ,  G01R1/16 ,  G11C29/56

Abstract: In some embodiments, a semiconductor wafer testing system is provided. The semiconductor wafer testing system includes a semiconductor wafer prober having one or more conductive probes, where the semiconductor wafer prober is configured to position the one or more conductive probes on an integrated chip (IC) that is disposed on a semiconductor wafer. The semiconductor wafer testing system also includes a ferromagnetic wafer chuck, where the ferromagnetic wafer chuck is configured to hold the semiconductor wafer while the wafer prober positions the one or more conductive probes on the IC. An upper magnet is disposed over the ferromagnetic wafer chuck, where the upper magnet is configured to generate an external magnetic field between the upper magnet and the ferromagnetic wafer chuck, and where the ferromagnetic wafer chuck amplifies the external magnetic field such that the external magnetic field passes through the IC with an amplified magnetic field strength.

公开(公告)号：US12040036B2

公开(公告)日：2024-07-16

申请号：US18362525

申请日：2023-07-31

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chia-Hsiang Chen ,  Chih-Yang Chang ,  Chia Yu Wang ,  Meng-Chun Shih

IPC: G11C29/44 ,  G11C29/12 ,  G11C29/46

CPC classification number: G11C29/4401 ,  G11C29/12005 ,  G11C29/12015 ,  G11C29/46

Abstract: The present disclosure describes a magnetic memory device. The magnetic memory device includes a magnetic sensing array configured to sense an external magnetic field strength. The magnetic memory device further includes a voltage modulator configured to, in response to the external magnetic field strength being greater than a threshold magnetic field strength, provide a test voltage different from a current write voltage of the magnetic memory device. The magnetic memory device further includes an error check array configured to use the test voltage as a write voltage of the error check array and provide a bit error rate corresponding to the test voltage. The magnetic memory device further includes a control unit configured to adjust, based on the bit error rate being equal to or less than a threshold bit error rate, a write voltage of the magnetic memory device from the current write voltage to the test voltage.

公开(公告)号：US20230410932A1

公开(公告)日：2023-12-21

申请号：US18362525

申请日：2023-07-31

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chia-Hsiang CHEN ,  Chih-Yang Chang ,  Chia Yu Wang ,  Meng-Chun Shih

IPC: G11C29/44 ,  G11C29/46 ,  G11C29/12

CPC classification number: G11C29/4401 ,  G11C29/46 ,  G11C29/12005 ,  G11C29/12015

Abstract: The present disclosure describes a magnetic memory device. The magnetic memory device includes a magnetic sensing array configured to sense an external magnetic field strength. The magnetic memory device further includes a voltage modulator configured to, in response to the external magnetic field strength being greater than a threshold magnetic field strength, provide a test voltage different from a current write voltage of the magnetic memory device. The magnetic memory device further includes an error check array configured to use the test voltage as a write voltage of the error check array and provide a bit error rate corresponding to the test voltage. The magnetic memory device further includes a control unit configured to adjust, based on the bit error rate being equal to or less than a threshold bit error rate, a write voltage of the magnetic memory device from the current write voltage to the test voltage.

公开(公告)号：US20200097255A1

公开(公告)日：2020-03-26

申请号：US16434345

申请日：2019-06-07

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Harry-Hak-Lay Chuang ,  Chih-Yang Chang ,  Ching-Huang Wang ,  Chih-Hui Weng ,  Tien-Wei Chiang ,  Meng-Chun Shih ,  Chia Yu Wang ,  Chia-Hsiang Chen

IPC: G06F7/58 ,  G11C11/16

Abstract: In some embodiments, a method for generating a random bit is provided. The method includes generating a first random bit by providing a random number generator (RNG) signal to a magnetoresistive random-access memory (MRAM) cell. The RNG signal has a probability of about 0.5 to switch the resistive state of the MRAM cell from a first resistive state corresponding to a first data state to a second resistive state corresponding to a second data sate. The first random bit is then read from the MRAM cell.

公开(公告)号：US20200096559A1

公开(公告)日：2020-03-26

申请号：US16411647

申请日：2019-05-14

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Harry-Hak-Lay Chuang ,  Chih-Yang Chang ,  Ching-Huang Wang ,  Tien-Wei Chiang ,  Meng-Chun Shih ,  Chia Yu Wang

IPC: G01R31/28 ,  G11C11/16 ,  G11C29/56 ,  G01R1/16

Abstract: In some embodiments, a semiconductor wafer testing system is provided. The semiconductor wafer testing system includes a semiconductor wafer prober having one or more conductive probes, where the semiconductor wafer prober is configured to position the one or more conductive probes on an integrated chip (IC) that is disposed on a semiconductor wafer. The semiconductor wafer testing system also includes a ferromagnetic wafer chuck, where the ferromagnetic wafer chuck is configured to hold the semiconductor wafer while the wafer prober positions the one or more conductive probes on the IC. An upper magnet is disposed over the ferromagnetic wafer chuck, where the upper magnet is configured to generate an external magnetic field between the upper magnet and the ferromagnetic wafer chuck, and where the ferromagnetic wafer chuck amplifies the external magnetic field such that the external magnetic field passes through the IC with an amplified magnetic field strength.