公开(公告)号：US12040036B2

公开(公告)日：2024-07-16

申请号：US18362525

申请日：2023-07-31

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chia-Hsiang Chen ,  Chih-Yang Chang ,  Chia Yu Wang ,  Meng-Chun Shih

IPC: G11C29/44 ,  G11C29/12 ,  G11C29/46

CPC classification number: G11C29/4401 ,  G11C29/12005 ,  G11C29/12015 ,  G11C29/46

Abstract: The present disclosure describes a magnetic memory device. The magnetic memory device includes a magnetic sensing array configured to sense an external magnetic field strength. The magnetic memory device further includes a voltage modulator configured to, in response to the external magnetic field strength being greater than a threshold magnetic field strength, provide a test voltage different from a current write voltage of the magnetic memory device. The magnetic memory device further includes an error check array configured to use the test voltage as a write voltage of the error check array and provide a bit error rate corresponding to the test voltage. The magnetic memory device further includes a control unit configured to adjust, based on the bit error rate being equal to or less than a threshold bit error rate, a write voltage of the magnetic memory device from the current write voltage to the test voltage.

公开(公告)号：US20190386061A1

公开(公告)日：2019-12-19

申请号：US16379901

申请日：2019-04-10

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kuo-An Liu ,  Chung-Cheng Wu ,  Harry-Hak-Lay Chuang ,  Gwan-Sin Chang ,  Tien-Wei Chiang ,  Zhiqiang Wu ,  Chia-Hsiang Chen

IPC: H01L27/22 ,  H01L43/08 ,  H01L43/02

Abstract: In some embodiments, the present application provides a memory device. The memory device includes a chip that includes a magnetic random access memory (MRAM) cell. A magnetic-field-shielding structure comprised of conductive or magnetic material at least partially surrounds the chip. The magnetic-field-shielding structure comprises a sidewall region that laterally surrounds the chip, an upper region extending upward from the sidewall region, and a lower region extending downward from the sidewall region. At least one of the upper region and/or lower region terminate at an opening over the chip.

公开(公告)号：US11088083B2

公开(公告)日：2021-08-10

申请号：US16381410

申请日：2019-04-11

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Harry-Hak-Lay Chuang ,  Tien-Wei Chiang ,  Kuo-An Liu ,  Chia-Hsiang Chen

IPC: H01L27/22 ,  H01L23/552 ,  H01L43/02 ,  H01L43/12 ,  H01L23/495 ,  H01L23/00

Abstract: In some embodiments, the present application provides a memory device. The memory device includes a chip that includes a magnetic random access memory (MRAM) cell. A magnetic-field-shielding structure at least partially surrounding the chip including a multilayer stack. The multilayer stack includes a magnetic layer and a dielectric layer. A first magnetic region is located inside an inner surface of the magnetic field shielding structure and a second magnetic region is located immediately outside an outer surface of the magnetic field shielding structure. A magnetic field in the first magnetic region is less than a magnetic field in the second magnetic region.

公开(公告)号：US11531524B2

公开(公告)日：2022-12-20

申请号：US16434345

申请日：2019-06-07

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Harry-Hak-Lay Chuang ,  Chih-Yang Chang ,  Ching-Huang Wang ,  Chih-Hui Weng ,  Tien-Wei Chiang ,  Meng-Chun Shih ,  Chia Yu Wang ,  Chia-Hsiang Chen

IPC: G06F7/58 ,  G11C11/16

Abstract: In some embodiments, a method for generating a random bit is provided. The method includes generating a first random bit by providing a random number generator (RNG) signal to a magnetoresistive random-access memory (MRAM) cell. The RNG signal has a probability of about 0.5 to switch the resistive state of the MRAM cell from a first resistive state corresponding to a first data state to a second resistive state corresponding to a second data state. The first random bit is then read from the MRAM cell.

公开(公告)号：US11139341B2

公开(公告)日：2021-10-05

申请号：US16379901

申请日：2019-04-10

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kuo-An Liu ,  Chung-Cheng Wu ,  Harry-Hak-Lay Chuang ,  Gwan-Sin Chang ,  Tien-Wei Chiang ,  Zhiqiang Wu ,  Chia-Hsiang Chen

IPC: H01L27/22 ,  H01L43/08 ,  H01L43/02 ,  G11C11/16

Abstract: In some embodiments, the present application provides a memory device. The memory device includes a chip that includes a magnetic random access memory (MRAM) cell. A magnetic-field-shielding structure comprised of conductive or magnetic material at least partially surrounds the chip. The magnetic-field-shielding structure comprises a sidewall region that laterally surrounds the chip, an upper region extending upward from the sidewall region, and a lower region extending downward from the sidewall region. At least one of the upper region and/or lower region terminate at an opening over the chip.

公开(公告)号：US11837312B1

公开(公告)日：2023-12-05

申请号：US17807967

申请日：2022-06-21

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chia-Hsiang Chen ,  Chih-Yang Chang ,  Chia Yu Wang ,  Meng-Chun Shih

IPC: G11C29/44 ,  G11C29/12 ,  G11C29/46

CPC classification number: G11C29/4401 ,  G11C29/12005 ,  G11C29/12015 ,  G11C29/46

Abstract: The present disclosure describes a magnetic memory device. The magnetic memory device includes a magnetic sensing array configured to sense an external magnetic field strength. The magnetic memory device further includes a voltage modulator configured to, in response to the external magnetic field strength being greater than a threshold magnetic field strength, provide a test voltage different from a current write voltage of the magnetic memory device. The magnetic memory device further includes an error check array configured to use the test voltage as a write voltage of the error check array and provide a bit error rate corresponding to the test voltage. The magnetic memory device further includes a control unit configured to adjust, based on the bit error rate being equal to or less than a threshold bit error rate, a write voltage of the magnetic memory device from the current write voltage to the test voltage.

公开(公告)号：US11276649B2

公开(公告)日：2022-03-15

申请号：US16711152

申请日：2019-12-11

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Harry-Hak-Lay Chuang ,  Tien-Wei Chiang ,  Chia-Hsiang Chen ,  Meng-Chun Shih ,  Ching-Huang Wang

IPC: H01L23/552 ,  H05K9/00 ,  H01L43/02

Abstract: Devices and methods are provided in which a magnetic sensitive semiconductor chip, such as a magnetoresistive random-access memory (MRAM) chip, is shielded from magnetic interference by a magnetic shielding layer. A device includes a housing that defines an exterior surface. A semiconductor chip is disposed within the housing, and the semiconductor chip is spaced apart from the exterior surface of the housing. A magnetic shielding layer is spaced apart from the semiconductor chip by a distance less than 5 mm.

公开(公告)号：US20200097255A1

公开(公告)日：2020-03-26

申请号：US16434345

申请日：2019-06-07

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Harry-Hak-Lay Chuang ,  Chih-Yang Chang ,  Ching-Huang Wang ,  Chih-Hui Weng ,  Tien-Wei Chiang ,  Meng-Chun Shih ,  Chia Yu Wang ,  Chia-Hsiang Chen

IPC: G06F7/58 ,  G11C11/16

Abstract: In some embodiments, a method for generating a random bit is provided. The method includes generating a first random bit by providing a random number generator (RNG) signal to a magnetoresistive random-access memory (MRAM) cell. The RNG signal has a probability of about 0.5 to switch the resistive state of the MRAM cell from a first resistive state corresponding to a first data state to a second resistive state corresponding to a second data sate. The first random bit is then read from the MRAM cell.

公开(公告)号：US20200006245A1

公开(公告)日：2020-01-02

申请号：US16381410

申请日：2019-04-11

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Harry-Hak-Lay Chuang ,  Tien-Wei Chiang ,  Kuo-An Liu ,  Chia-Hsiang Chen

IPC: H01L23/552 ,  H01L27/22 ,  H01L43/02 ,  H01L43/12 ,  H01L23/495 ,  H01L23/00

Abstract: In some embodiments, the present application provides a memory device. The memory device includes a chip that includes a magnetic random access memory (MRAM) cell. A magnetic-field-shielding structure at least partially surrounding the chip including a multilayer stack. The multilayer stack includes a magnetic layer and a dielectric layer. A first magnetic region is located inside an inner surface of the magnetic field shielding structure and a second magnetic region is located immediately outside an outer surface of the magnetic field shielding structure. A magnetic field in the first magnetic region is less than a magnetic field in the second magnetic region