公开(公告)号：US11531524B2

公开(公告)日：2022-12-20

申请号：US16434345

申请日：2019-06-07

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Harry-Hak-Lay Chuang ,  Chih-Yang Chang ,  Ching-Huang Wang ,  Chih-Hui Weng ,  Tien-Wei Chiang ,  Meng-Chun Shih ,  Chia Yu Wang ,  Chia-Hsiang Chen

IPC: G06F7/58 ,  G11C11/16

Abstract: In some embodiments, a method for generating a random bit is provided. The method includes generating a first random bit by providing a random number generator (RNG) signal to a magnetoresistive random-access memory (MRAM) cell. The RNG signal has a probability of about 0.5 to switch the resistive state of the MRAM cell from a first resistive state corresponding to a first data state to a second resistive state corresponding to a second data state. The first random bit is then read from the MRAM cell.

公开(公告)号：US11506706B2

公开(公告)日：2022-11-22

申请号：US17126222

申请日：2020-12-18

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Harry-Hak-Lay Chuang ,  Chih-Yang Chang ,  Ching-Huang Wang ,  Tien-Wei Chiang ,  Meng-Chun Shih ,  Chia Yu Wang

IPC: G01R31/26 ,  G01R31/28 ,  G11C11/16 ,  G01R1/16 ,  G11C29/56

Abstract: In some embodiments, a semiconductor wafer testing system is provided. The semiconductor wafer testing system includes a semiconductor wafer prober having one or more conductive probes, where the semiconductor wafer prober is configured to position the one or more conductive probes on an integrated chip (IC) that is disposed on a semiconductor wafer. The semiconductor wafer testing system also includes a ferromagnetic wafer chuck, where the ferromagnetic wafer chuck is configured to hold the semiconductor wafer while the wafer prober positions the one or more conductive probes on the IC. An upper magnet is disposed over the ferromagnetic wafer chuck, where the upper magnet is configured to generate an external magnetic field between the upper magnet and the ferromagnetic wafer chuck, and where the ferromagnetic wafer chuck amplifies the external magnetic field such that the external magnetic field passes through the IC with an amplified magnetic field strength.

公开(公告)号：US10176998B2

公开(公告)日：2019-01-08

申请号：US15496080

申请日：2017-04-25

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chun-Yu Wu ,  Meng-Chun Shih ,  Chin-Huang Wang

IPC: H01L21/28 ,  H01L21/324 ,  H01L21/326 ,  H01L29/788

Abstract: A semiconductor device includes a substrate, a dielectric layer and a floating gate. The dielectric layer disposed on the substrate. The floating gate disposed on the dielectric layer. After a first programming process, the floating gate is configured to store first electrons that are to be combined with ions from the dielectric layer. After a second programming process, the floating gate is configured to store second electrons, and a number of the second electrons is larger than a number of the first electrons.

公开(公告)号：US11837312B1

公开(公告)日：2023-12-05

申请号：US17807967

申请日：2022-06-21

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chia-Hsiang Chen ,  Chih-Yang Chang ,  Chia Yu Wang ,  Meng-Chun Shih

IPC: G11C29/44 ,  G11C29/12 ,  G11C29/46

CPC classification number: G11C29/4401 ,  G11C29/12005 ,  G11C29/12015 ,  G11C29/46

Abstract: The present disclosure describes a magnetic memory device. The magnetic memory device includes a magnetic sensing array configured to sense an external magnetic field strength. The magnetic memory device further includes a voltage modulator configured to, in response to the external magnetic field strength being greater than a threshold magnetic field strength, provide a test voltage different from a current write voltage of the magnetic memory device. The magnetic memory device further includes an error check array configured to use the test voltage as a write voltage of the error check array and provide a bit error rate corresponding to the test voltage. The magnetic memory device further includes a control unit configured to adjust, based on the bit error rate being equal to or less than a threshold bit error rate, a write voltage of the magnetic memory device from the current write voltage to the test voltage.

公开(公告)号：US20210109152A1

公开(公告)日：2021-04-15

申请号：US17126222

申请日：2020-12-18

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Harry-Hak-Lay Chuang ,  Chih-Yang Chang ,  Ching-Huang Wang ,  Tien-Wei Chiang ,  Meng-Chun Shih ,  Chia Yu Wang

IPC: G01R31/28 ,  G01R1/16 ,  G11C11/16 ,  G11C29/56

Abstract: In some embodiments, a semiconductor wafer testing system is provided. The semiconductor wafer testing system includes a semiconductor wafer prober having one or more conductive probes, where the semiconductor wafer prober is configured to position the one or more conductive probes on an integrated chip (IC) that is disposed on a semiconductor wafer. The semiconductor wafer testing system also includes a ferromagnetic wafer chuck, where the ferromagnetic wafer chuck is configured to hold the semiconductor wafer while the wafer prober positions the one or more conductive probes on the IC. An upper magnet is disposed over the ferromagnetic wafer chuck, where the upper magnet is configured to generate an external magnetic field between the upper magnet and the ferromagnetic wafer chuck, and where the ferromagnetic wafer chuck amplifies the external magnetic field such that the external magnetic field passes through the IC with an amplified magnetic field strength.

公开(公告)号：US10665321B2

公开(公告)日：2020-05-26

申请号：US15690303

申请日：2017-08-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chia-Yu Wang ,  Ching-Huang Wang ,  Chun-Jung Lin ,  Tien-Wei Chiang ,  Meng-Chun Shih ,  Kuei-Hung Shen

IPC: G11C29/00 ,  G11C29/56 ,  G11C29/50 ,  G11C11/16 ,  H01L27/22 ,  G11C29/44 ,  G11C29/04 ,  G11C29/10

Abstract: The disclosure is related a method for testing a magnetic memory device and a test apparatus are provided. In some exemplary embodiments, the method includes at least the following steps. The magnetic memory device is initialized by applying a first magnetic field to force write a first data to the magnetic memory device. Then, a second magnetic field is applied to the magnetic memory device. Second data may be obtained from the magnetic memory device by performing a chip probing process. Accordingly, performance of the magnetic memory device may be determined based on the second data.

公开(公告)号：US12040036B2

公开(公告)日：2024-07-16

申请号：US18362525

申请日：2023-07-31

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chia-Hsiang Chen ,  Chih-Yang Chang ,  Chia Yu Wang ,  Meng-Chun Shih

IPC: G11C29/44 ,  G11C29/12 ,  G11C29/46

CPC classification number: G11C29/4401 ,  G11C29/12005 ,  G11C29/12015 ,  G11C29/46

Abstract: The present disclosure describes a magnetic memory device. The magnetic memory device includes a magnetic sensing array configured to sense an external magnetic field strength. The magnetic memory device further includes a voltage modulator configured to, in response to the external magnetic field strength being greater than a threshold magnetic field strength, provide a test voltage different from a current write voltage of the magnetic memory device. The magnetic memory device further includes an error check array configured to use the test voltage as a write voltage of the error check array and provide a bit error rate corresponding to the test voltage. The magnetic memory device further includes a control unit configured to adjust, based on the bit error rate being equal to or less than a threshold bit error rate, a write voltage of the magnetic memory device from the current write voltage to the test voltage.

公开(公告)号：US20230410932A1

公开(公告)日：2023-12-21

申请号：US18362525

申请日：2023-07-31

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chia-Hsiang CHEN ,  Chih-Yang Chang ,  Chia Yu Wang ,  Meng-Chun Shih

IPC: G11C29/44 ,  G11C29/46 ,  G11C29/12

CPC classification number: G11C29/4401 ,  G11C29/46 ,  G11C29/12005 ,  G11C29/12015

Abstract: The present disclosure describes a magnetic memory device. The magnetic memory device includes a magnetic sensing array configured to sense an external magnetic field strength. The magnetic memory device further includes a voltage modulator configured to, in response to the external magnetic field strength being greater than a threshold magnetic field strength, provide a test voltage different from a current write voltage of the magnetic memory device. The magnetic memory device further includes an error check array configured to use the test voltage as a write voltage of the error check array and provide a bit error rate corresponding to the test voltage. The magnetic memory device further includes a control unit configured to adjust, based on the bit error rate being equal to or less than a threshold bit error rate, a write voltage of the magnetic memory device from the current write voltage to the test voltage.

公开(公告)号：US20190066820A1

公开(公告)日：2019-02-28

申请号：US15690303

申请日：2017-08-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chia-Yu Wang ,  Ching-Huang Wang ,  Chun-Jung Lin ,  Tien-Wei Chiang ,  Meng-Chun Shih ,  Kuei-Hung Shen

IPC: G11C29/56 ,  G11C29/50 ,  G11C11/16 ,  H01L27/22

Abstract: The disclosure is related a method for testing a magnetic memory device and a test apparatus are provided. In some exemplary embodiments, the method includes at least the following steps. The magnetic memory device is initialized by applying a first magnetic field to force write a first data to the magnetic memory device. Then, a second magnetic field is applied to the magnetic memory device. Second data may be obtained from the magnetic memory device by performing a chip probing process. Accordingly, performance of the magnetic memory device may be determined based on the second data.

公开(公告)号：US11276649B2

公开(公告)日：2022-03-15

申请号：US16711152

申请日：2019-12-11

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Harry-Hak-Lay Chuang ,  Tien-Wei Chiang ,  Chia-Hsiang Chen ,  Meng-Chun Shih ,  Ching-Huang Wang

IPC: H01L23/552 ,  H05K9/00 ,  H01L43/02

Abstract: Devices and methods are provided in which a magnetic sensitive semiconductor chip, such as a magnetoresistive random-access memory (MRAM) chip, is shielded from magnetic interference by a magnetic shielding layer. A device includes a housing that defines an exterior surface. A semiconductor chip is disposed within the housing, and the semiconductor chip is spaced apart from the exterior surface of the housing. A magnetic shielding layer is spaced apart from the semiconductor chip by a distance less than 5 mm.