公开(公告)号：US20210210616A1

公开(公告)日：2021-07-08

申请号：US17157180

申请日：2021-01-25

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： I-Chih CHEN ,  Ru-Shang HSIAO ,  Ching-Pin LIN ,  Chih-Mu HUANG ,  Fu-Tsun TSAI

IPC: H01L29/66 ,  H01L27/088 ,  H01L21/8234 ,  H01L29/423

Abstract: A semiconductor device includes: first and second fin structures, disposed on a substrate, that respectively extend in parallel to an axis; a first gate feature that traverses the first fin structure to overlay a central portion of the first fin structure; a second gate feature that traverses the second fin structure to overlay a central portion of the second fin structure; a first spacer comprising: a first portion comprising two layers that respectively extend from sidewalls of the first gate feature toward opposite directions of the axis; and a second portion comprising two layers that respectively extend from sidewalls of the first portion of the first spacer toward the opposite directions of the axis; and a second spacer comprising two layers that respectively extend from sidewalls of the second gate feature toward the opposite directions of the axis.

公开(公告)号：US20150132919A1

公开(公告)日：2015-05-14

申请号：US14080631

申请日：2013-11-14

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Fu-Cheng CHANG ,  Chai-Der YEN ,  Fu-Tsun TSAI ,  Chi-Cherng JENG ,  Chih-Mu HUANG

IPC: H01L21/762 ,  G03F1/00

CPC classification number: H01L21/76229 ,  G03F1/00 ,  H01L21/0274 ,  H01L21/3083

Abstract: In a method for manufacturing a dual shallow trench isolation structure, a substrate is provided, and a mask layer is formed on the substrate. The mask layer is patterned by using a photomask to form at least one first hole and at least one second hole in the mask layer, in which a depth of the at least one first hole is different from a depth of the at least one second hole. The mask layer and the substrate are etched to form at least one first trench having a first depth and at least one second trench having a second depth, in which the first depth is different from the second depth. The remaining mask layer is removed. A first isolation layer and A second isolation layer are respectively formed in the at least one first trench and the at least one second trench.

Abstract translation: 在制造双浅沟槽隔离结构的方法中，提供衬底，并且在衬底上形成掩模层。 通过使用光掩模来对掩模层进行构图，以在掩模层中形成至少一个第一孔和至少一个第二孔，其中至少一个第一孔的深度与至少一个第二孔的深度不同 。 蚀刻掩模层和衬底以形成具有第一深度的至少一个第一沟槽和具有第二深度的至少一个第二沟槽，其中第一深度不同于第二深度。 剩下的掩模层被去除。 第一隔离层和第二隔离层分别形成在至少一个第一沟槽和至少一个第二沟槽中。

公开(公告)号：US20200295188A1

公开(公告)日：2020-09-17

申请号：US16892458

申请日：2020-06-04

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Jung-Chi JENG ,  I-Chih CHEN ,  Wen-Chang KUO ,  Ying-Hao CHEN ,  Ru-Shang HSIAO ,  Chih-Mu HUANG

IPC: H01L29/78 ,  H01L29/06 ,  H01L29/66

Abstract: A method for forming a semiconductor device is provided. The method includes forming an isolation structure in a semiconductor substrate. The method includes forming a gate over the semiconductor substrate. The method includes forming a support film over the isolation structure. The support film is a continuous film which continuously covers the isolation structure and the gate over the isolation structure, the support film conformally covers a first portion of a top surface and a second portion of a first sidewall of the gate, the top surface faces away from the semiconductor substrate, the support film and a topmost surface of the active region do not overlap with each other, and the topmost surface faces the gate. The method includes after forming the support film, forming lightly doped regions in the semiconductor substrate and at two opposite sides of the gate.

公开(公告)号：US20200035821A1

公开(公告)日：2020-01-30

申请号：US16405057

申请日：2019-05-07

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ting-Chun KUAN ,  I-Chih CHEN ,  Chih-Mu HUANG ,  Fu-Tsun TSAI ,  Sheng-Lin HSIEH ,  Kuan-Jung CHEN

IPC: H01L29/78 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/66 ,  H01L21/768 ,  H01L21/02

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a substrate and a gate structure over the substrate. The semiconductor device structure also includes a source/drain feature in the substrate, protruding from the substrate, and on a sidewall surface of the gate structure. The semiconductor device structure also includes an insulating barrier structure in the substrate and partially covering the bottom and sidewalls of the source/drain feature.

公开(公告)号：US20160225630A1

公开(公告)日：2016-08-04

申请号：US14795299

申请日：2015-07-09

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Ru-Shang HSIAO ,  Chi-Cherng JENG ,  Chih-Mu HUANG ,  Shin-Yeu TSAI ,  Fang-Wei LIN

IPC: H01L21/3065 ,  H01L21/308 ,  H01L21/283

CPC classification number: H01L21/3065 ,  H01L21/02068 ,  H01L21/283 ,  H01L21/28518 ,  H01L21/3003 ,  H01L21/3081 ,  H01L21/47635 ,  H01L21/76826 ,  H01L21/76829 ,  H01L21/76834 ,  H01L21/76843 ,  H01L21/76855 ,  H01L21/76883 ,  H01L21/82345 ,  H01L29/66545

Abstract: A method for forming a semiconductor device structure is provided. The method includes forming a metal gate stack over a semiconductor substrate. The method also includes performing a hydrogen-containing plasma treatment on the metal gate stack to modify a surface of the metal gate stack. The hydrogen-containing plasma treatment includes exciting a gas mixture including a first hydrogen-containing gas and a second hydrogen-containing gas to generate a hydrogen-containing plasma.

Abstract translation: 提供一种形成半导体器件结构的方法。 该方法包括在半导体衬底上形成金属栅叠层。 该方法还包括在金属栅极叠层上执行含氢等离子体处理以改变金属栅极叠层的表面。 含氢等离子体处理包括激发包括第一含氢气体和第二含氢气体的气体混合物以产生含氢等离子体。

公开(公告)号：US20250072082A1

公开(公告)日：2025-02-27

申请号：US18938087

申请日：2024-11-05

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： I-Chih CHEN ,  Ru-Shang HSIAO ,  Ching-Pin LIN ,  Chih-Mu HUANG ,  Fu-Tsun TSAI

IPC: H01L29/66 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/423

Abstract: A semiconductor device includes: first and second fin structures, disposed on a substrate, that respectively extend in parallel to an axis; a first gate feature that traverses the first fin structure to overlay a central portion of the first fin structure; a second gate feature that traverses the second fin structure to overlay a central portion of the second fin structure; a first spacer comprising: a first portion comprising two layers that respectively extend from sidewalls of the first gate feature toward opposite directions of the axis; and a second portion comprising two layers that respectively extend from sidewalls of the first portion of the first spacer toward the opposite directions of the axis; and a second spacer comprising two layers that respectively extend from sidewalls of the second gate feature toward the opposite directions of the axis.

公开(公告)号：US20150129987A1

公开(公告)日：2015-05-14

申请号：US14080313

申请日：2013-11-14

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Jung-Chi JENG ,  I-Chih CHEN ,  Wen-Chang KUO ,  Ying-Hao CHEN ,  Ru-Shang HSIAO ,  Chih-Mu HUANG

IPC: H01L29/78 ,  H01L29/06 ,  H01L21/02 ,  H01L29/66

CPC classification number: H01L29/7833 ,  H01L29/0649 ,  H01L29/6659

Abstract: Embodiments of mechanisms for forming a semiconductor device are provided. The semiconductor device includes a semiconductor substrate and an isolation structure in the semiconductor substrate and surrounding an active region of the semiconductor substrate. The semiconductor device also includes a gate over the semiconductor substrate, and the gate has an intermediate portion over the active region and two end portions connected to the intermediate portion, and the end portions are over the isolation structure. The semiconductor device further includes a support film over the isolation structure and covering the isolation structure and at least one of the end portions of the gate. The support film exposes the active region and the intermediate portion of the gate.

Abstract translation: 提供了用于形成半导体器件的机构的实施例。 半导体器件包括半导体衬底和半导体衬底中的隔离结构，并围绕半导体衬底的有源区。 半导体器件还包括半导体衬底上的栅极，并且栅极具有在有源区上方的中间部分和连接到中间部分的两个端部，并且端部在隔离结构上方。 半导体器件还包括隔离结构上的支撑膜，并覆盖隔离结构和栅极的至少一个端部。 支撑膜暴露栅极的有源区域和中间部分。

公开(公告)号：US20180061987A1

公开(公告)日：2018-03-01

申请号：US15804887

申请日：2017-11-06

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD

Inventor： I-Chih CHEN ,  Ying-Lang WANG ,  Chih-Mu HUANG ,  Ying-Hao CHEN ,  Wen-Chang KUO ,  Jung-Chi JENG

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/08 ,  H01L29/167 ,  H01L29/165

Abstract: A method of fabricating a semiconductor device includes following steps. A trench is formed in a substrate. A barrier layer and an epitaxy layer are formed in sequence in the trench. The barrier layer has a first dopant. A source/drain recess cavity is formed by etching at least the epitaxial layer. A source/drain region is formed in the source/drain recess cavity. The source/drain region has a second dopant.

公开(公告)号：US20170338342A1

公开(公告)日：2017-11-23

申请号：US15670978

申请日：2017-08-07

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Jung-Chi JENG ,  I-Chih CHEN ,  Wen-Chang KUO ,  Ying-Hao CHEN ,  Ru-Shang HSIAO ,  Chih-Mu HUANG

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/06

CPC classification number: H01L29/7833 ,  H01L29/0649 ,  H01L29/6659

Abstract: A method for forming a semiconductor device is provided. The method includes forming an isolation structure in a semiconductor substrate, and the isolation structure surrounds an active region of the semiconductor substrate. The method also includes forming a gate over the semiconductor substrate, and the gate is across the active region and extends onto the isolation structure. The gate has an intermediate portion over the active region and two end portions connected to the intermediate portion, the end portions are over the isolation structure. The method includes forming a support film over the isolation structure, and the support film is a continuous film which continuously covers the isolation structure and at least one end portion of the gate.

公开(公告)号：US20170317164A1

公开(公告)日：2017-11-02

申请号：US15651751

申请日：2017-07-17

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： I-Chih CHEN ,  Chih-Mu HUANG ,  Fu-Tsun TSAI ,  Meng-Yi WU ,  Yung-Fa LEE ,  Ying-Lang WANG

IPC: H01L29/06 ,  H01L29/78 ,  H01L29/66 ,  H01L29/08 ,  H01L21/265

CPC classification number: H01L29/0638 ,  H01L21/26506 ,  H01L29/0603 ,  H01L29/0847 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/7834 ,  H01L29/7848

Abstract: A semiconductor device includes a semiconductor substrate having a first conductivity type region including a first conductivity type impurity. A first gate structure is on the semiconductor substrate overlying the first conductivity type region. A second conductivity type region including a second conductivity type impurity is formed in the semiconductor substrate. A barrier layer is located between the first conductivity type region and the second conductivity type region. The barrier layer prevents diffusion of the second conductivity type impurity from the second conductivity type region into the first conductivity type region.