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公开(公告)号：US20200091423A1
公开(公告)日：2020-03-19
申请号：US16688976
申请日：2019-11-19
发明人： Chun-Hsu YEN , Yu-Chuan Hsu , Chen-Hui Yang
摘要： A method for making a memory device, includes: forming a first dielectric layer over a bottom electrode; forming a first void extending through the first dielectric layer to expose a portion of an upper boundary of the bottom electrode; forming a first conductive structure lining along respective sidewalls of the first void and the exposed portion of the upper boundary of the bottom electrode; filling the first void with the first dielectric layer; and forming a phase change material layer over the first dielectric layer to cause the phase change material layer to contact at least a portion of a sidewall of the first conductive structure.
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公开(公告)号：US20220140235A1
公开(公告)日：2022-05-05
申请号：US17571260
申请日：2022-01-07
发明人： Chun-Hsu YEN , Yu-Chuan HSU , Chen-Hui YANG
摘要： A method for making a memory device, includes: forming a first dielectric layer over a bottom electrode; forming a first void extending through the first dielectric layer to expose a portion of an upper boundary of the bottom electrode; forming a first conductive structure lining along respective sidewalls of the first void and the exposed portion of the upper boundary of the bottom electrode; filling the first void with the first dielectric layer; and forming a phase change material layer over the first dielectric layer to cause the phase change material layer to contact at least a portion of a sidewall of the first conductive structure.
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公开(公告)号：US20240365690A1
公开(公告)日：2024-10-31
申请号：US18770547
申请日：2024-07-11
发明人： Chun-Hsu YEN , Yu-Chuan HSU , Chen-Hui YANG
CPC分类号： H10N70/8413 , H10B63/30 , H10N70/011 , H10N70/063 , H10N70/231 , H10N70/8265 , H10N70/8825 , H10N70/8828 , H10N70/884 , G11C13/0004 , H10B63/84 , H10N70/041 , H10N70/066 , H10N70/826 , H10N70/841 , H10N70/881 , H10N70/8833
摘要： A method for making a memory device, includes: forming a first dielectric layer over a bottom electrode; forming a first void extending through the first dielectric layer to expose a portion of an upper boundary of the bottom electrode; forming a first conductive structure lining along respective sidewalls of the first void and the exposed portion of the upper boundary of the bottom electrode; filling the first void with the first dielectric layer; and forming a phase change material layer over the first dielectric layer to cause the phase change material layer to contact at least a portion of a sidewall of the first conductive structure.
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4.发明申请METHOD FOR FABRICATING SHALLOW TRENCH ISOLATION AND SEMICONDUCTOR STRUCTURE USING THE SAME 有权使用该方法制造低温分离分离和半导体结构公开(公告)号：US20160254179A1
公开(公告)日：2016-09-01
申请号：US14632690
申请日：2015-02-26
发明人： Chun-Hsu YEN , Bang-Yu HUANG , Chui-Ya PENG , Ching-Wen CHEN
IPC分类号： H01L21/762 , H01L29/06 , H01L21/311 , H01L21/02 , H01L21/3105
CPC分类号： H01L21/76224 , C23C16/045 , C23C16/505 , H01L21/02164 , H01L21/02211 , H01L21/02274 , H01L21/31053 , H01L21/31056 , H01L21/76229 , H01L29/0649
摘要： A method for fabricating a shallow trench isolation includes forming a trench in a substrate, forming a bottom shallow trench isolation dielectric filling a gap of the trench, and forming a top shallow trench isolation dielectric on the bottom shallow trench isolation. The bottom shallow trench isolation dielectric has a concave center portion, and the top shallow trench isolation dielectric is deposited on the bottom shallow trench isolation by a high density plasma chemical vapor deposition process using low deposition to sputter ratio. A semiconductor structure having the shallow trench isolation is also disclosed.
摘要翻译： 用于制造浅沟槽隔离的方法包括在衬底中形成沟槽，形成填充沟槽间隙的底部浅沟槽隔离电介质，以及在底部浅沟槽隔离件上形成顶部浅沟槽隔离电介质。 底部浅沟槽隔离电介质具有凹入的中心部分，并且通过使用低沉积溅射比的高密度等离子体化学气相沉积工艺将顶部浅沟槽隔离电介质沉积在底部浅沟槽隔离层上。 还公开了具有浅沟槽隔离的半导体结构。
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