公开(公告)号：US11532637B2

公开(公告)日：2022-12-20

申请号：US17132258

申请日：2020-12-23

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Jui-Yu Pan ,  Cheng-Bo Shu ,  Chung-Jen Huang ,  Jing-Ru Lin ,  Tsung-Yu Yang ,  Yun-Chi Wu ,  Yueh-Chieh Chu

IPC分类号： H01L27/11568 ,  H01L27/11582 ,  H01L49/02 ,  H01L21/311 ,  H01L29/66 ,  H01L29/792

摘要： Some embodiments relate to an integrated chip that includes a first source/drain region and a second source/drain region disposed in a substrate. A plane that is substantially perpendicular to an upper surface of the substrate traverses the first source/drain region and the second source/drain region. Agate electrode extends over a channel region in the substrate between the first source/drain region and the second source/drain region. The gate electrode is separated from the channel region by way of a charge trapping dielectric structure. The charge trapping dielectric structure includes a tunnel dielectric layer, a charge trapping dielectric layer over the tunnel dielectric layer, and a blocking dielectric layer over the charge trapping dielectric layer. The channel region has a channel width measured perpendicularly to the plane, and the tunnel dielectric layer has different thicknesses at different respective points along the channel width.

公开(公告)号：US11342025B2

公开(公告)日：2022-05-24

申请号：US16933718

申请日：2020-07-20

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

发明人： Yu-Wen Tseng ,  Tsung-Yu Yang ,  Chung-Jen Huang

IPC分类号： G11C16/00 ,  G11C16/10 ,  G11C16/04 ,  H01L27/11521 ,  G11C16/14 ,  H01L27/11526 ,  H01L29/788 ,  H01L27/11524 ,  H01L29/423

摘要： A memory unit includes a substrate and a floating gate memory cell. The floating gate memory cell includes an erase gate structure disposed on the substrate, floating gate structures select gates, a common source and drains. The common source is disposed in the substrate, and the erase gate structure is disposed on the common source. The floating gate structures protrude from recesses of the substrate at two opposite sides of the erase gate structure. A method for controlling the memory unit includes applying an erase gate programming voltage on the erase gate structure, applying a control gate programming voltage on the common source, applying a bit line programming voltage on the drains, and applying word line programming voltage on the select gates, in which the control gate programming voltage is greater than the erase gate programming voltage.

公开(公告)号：US20210111182A1

公开(公告)日：2021-04-15

申请号：US17132258

申请日：2020-12-23

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Jui-Yu Pan ,  Cheng-Bo Shu ,  Chung-Jen Huang ,  Jing-Ru Lin ,  Tsung-Yu Yang ,  Yun-Chi Wu ,  Yueh-Chieh Chu

IPC分类号： H01L27/11568 ,  H01L21/311 ,  H01L29/792 ,  H01L49/02 ,  H01L29/66 ,  H01L27/11582

摘要： Some embodiments relate to an integrated chip that includes a first source/drain region and a second source/drain region disposed in a substrate. A plane that is substantially perpendicular to an upper surface of the substrate traverses the first source/drain region and the second source/drain region. Agate electrode extends over a channel region in the substrate between the first source/drain region and the second source/drain region. The gate electrode is separated from the channel region by way of a charge trapping dielectric structure. The charge trapping dielectric structure includes a tunnel dielectric layer, a charge trapping dielectric layer over the tunnel dielectric layer, and a blocking dielectric layer over the charge trapping dielectric layer. The channel region has a channel width measured perpendicularly to the plane, and the tunnel dielectric layer has different thicknesses at different respective points along the channel width.

公开(公告)号：US11121047B2

公开(公告)日：2021-09-14

申请号：US16353044

申请日：2019-03-14

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

发明人： Cheng-Bo Shu ,  Tsung-Hua Yang ,  Chung-Jen Huang

IPC分类号： H01L23/58 ,  H01L21/66 ,  H01L23/522 ,  H01L27/02 ,  H01L23/528 ,  H01L21/78

摘要： A semiconductor structure includes a substrate, a device, a contact via, a metal/dielectric layer, and a test structure. The device is over the substrate. The contact via is connected to the device. The metal/dielectric layer is over the contact via. The metal/dielectric layer includes a first portion and a second portion. The first portion of the metal/dielectric layer has a metallization pattern connected to the contact via. The second portion of the metal/dielectric layer is void of metal. The test structure is over the second portion of the metal/dielectric layer.

公开(公告)号：US11024637B2

公开(公告)日：2021-06-01

申请号：US16271968

申请日：2019-02-11

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

发明人： Tsung-Yu Yang ,  Chung-Jen Huang

IPC分类号： H01L27/1157 ,  H01L29/66 ,  H01L21/3213 ,  H01L21/768 ,  H01L29/423 ,  H01L21/28 ,  H01L29/792 ,  H01L27/11573

摘要： A semiconductor device includes a semiconductor substrate and a pair of memory device structures. The semiconductor substrate includes a common source/drain region and a pair of individual source/drain regions, in which the common source/drain region is between the individual source/drain regions. The memory device structures each corresponds to one of the individual source/drain regions. Each memory device structure includes a trap storage structure, a control gate, a cap structure, and a word line. The trap storage structure is between the common source/drain region and the corresponding individual source/drain region. The control gate is over the trap storage structure. The cap structure is over the control gate, in which the cap structure comprises a nitride layer over the control gate and an oxide layer over the nitride layer. The word line is over the semiconductor substrate and laterally spaced from the control gate.

公开(公告)号：US10510765B2

公开(公告)日：2019-12-17

申请号：US15652310

申请日：2017-07-18

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

发明人： Yun-Chi Wu ,  Chung-Jen Huang

IPC分类号： H01L27/11568 ,  H01L21/8234 ,  H01L21/28 ,  H01L29/423 ,  H01L29/66 ,  H01L29/792 ,  H01L27/1157 ,  H01L27/11573

摘要： A memory device and a method for fabricating the same are provided. The memory device includes a semiconductor substrate, well regions, logic transistors, a high-voltage transistor, and a storage transistor. The well regions are disposed in the semiconductor substrate and include logic well regions, a high-voltage well region, and a memory well region. The logic transistors are disposed on the logic well regions. Each the logic transistors includes a high-k metal gate structure. The storage transistor is disposed on the memory well region, and includes a charge storage structure and a high-k metal gate structure. In the method for fabricating the memory device, a high-k first process or high-k last process is used for the formation of the high-k metal gate structures of the memory device. Because all the logic transistors and the storage transistor are formed with the high-k metal gate structure, a number of masks is decreased.

公开(公告)号：US10276728B2

公开(公告)日：2019-04-30

申请号：US15644506

申请日：2017-07-07

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

发明人： Cheng-Bo Shu ,  Yun-Chi Wu ,  Chung-Jen Huang

IPC分类号： H01L29/792 ,  H01L27/1157 ,  H01L29/06 ,  H01L29/423 ,  H01L29/786 ,  H01L29/66

摘要： A semiconductor device includes a non-volatile memory (NVM) cell. The NVM cell includes a semiconductor wire disposed over an insulating layer disposed on a substrate. The NVM cell includes a select transistor and a control transistor. The select transistor includes a gate dielectric layer disposed around the semiconductor wire and a select gate electrode disposed on the gate dielectric layer. The control transistor includes a stacked dielectric layer disposed around the semiconductor wire and a control gate electrode disposed on the stacked dielectric layer. The stacked dielectric layer includes a charge trapping layer. The select gate electrode is disposed adjacent to the control gate electrode with the stacked dielectric layer interposed therebetween.

公开(公告)号：US20180166451A1

公开(公告)日：2018-06-14

申请号：US15420232

申请日：2017-01-31

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

发明人： Tsung-Yu Yang ,  Chung-Jen Huang

IPC分类号： H01L27/1157 ,  H01L29/66 ,  H01L21/28 ,  H01L21/3213 ,  H01L21/768 ,  H01L29/423

CPC分类号： H01L27/1157 ,  H01L21/28282 ,  H01L21/32133 ,  H01L21/76895 ,  H01L27/11573 ,  H01L29/42344 ,  H01L29/66553 ,  H01L29/66833 ,  H01L29/792

摘要： In a method for manufacturing a semiconductor device, a cell well, a logic well and a high voltage well are formed in a first, a second and a third regions of a substrate. A first and a second stacked structures are formed on the first and second regions. A first and a second word line wells are formed in the cell well. First spacers are formed on sidewalls of the first and second stacked structures. A first gate oxide layer is formed on the third region and the first and second word line wells. A portion of the first stacked structure is removed to form a first and a second device structures. A second gate oxide layer is formed to cover the first, second and third regions. A first and a second word lines are formed adjacent to the first and second device structures.

公开(公告)号：US20180151586A1

公开(公告)日：2018-05-31

申请号：US15428260

申请日：2017-02-09

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

发明人： Yung-Chun Tu ,  Tsung-Yu Yang ,  Chung-Jen Huang

IPC分类号： H01L27/11568 ,  H01L23/535

CPC分类号： H01L23/535 ,  H01L27/1157 ,  H01L29/42344 ,  H01L29/792

摘要： A storage device includes a semiconductor substrate, a control gate, a word line, a dielectric layer, a charge storage nitride layer, and a blocking layer. The semiconductor substrate has a source region and a drain region. The control gate and a word line are disposed over the semiconductor substrate and located between the source and drain regions. The dielectric layer is in contact with the semiconductor substrate and disposed between the semiconductor substrate, the control gate, and the word line. The charge storage nitride layer is disposed between the dielectric layer and the control gate. The blocking layer is disposed between the charge storage nitride layer and the control gate.

公开(公告)号：US20180151585A1

公开(公告)日：2018-05-31

申请号：US15396886

申请日：2017-01-03

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

发明人： Cheng-Bo Shu ,  Tsung-Yu Yang ,  Chung-Jen Huang

IPC分类号： H01L27/11568 ,  H01L21/762 ,  H01L29/06 ,  H01L29/10 ,  H01L21/768 ,  H01L21/28 ,  H01L27/11573 ,  H01L29/51 ,  H01L29/66

CPC分类号： H01L27/11568 ,  H01L21/28185 ,  H01L21/28282 ,  H01L21/76224 ,  H01L21/76895 ,  H01L27/11573 ,  H01L29/0649 ,  H01L29/1095 ,  H01L29/42344 ,  H01L29/42364 ,  H01L29/513 ,  H01L29/518 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/66833

摘要： In a method for manufacturing a semiconductor device, a logic well and a high voltage well are respectively formed in second and third regions of a substrate. A first device structure and a second device structure are formed on a first region of the substrate, third and fourth device structures are respectively formed on the logic well and the high voltage well. A first word line Vt, a source side junction, and a second word line Vt are formed adjacent to the first device structure, between the first device structure and the second device structure, and adjacent to the second device structure. The fourth device structure is removed. A source line junction is formed in the source side junction. The third device structure is removed. First word line and second word lines are respectively formed on the first word line Vt and the second word line Vt.