公开(公告)号：US09496276B2

公开(公告)日：2016-11-15

申请号：US14092912

申请日：2013-11-27

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Harry Hak-Lay Chuang ,  Wei-Cheng Wu ,  Chang-Ming Wu ,  Shih-Chang Liu

IPC: H01L29/66 ,  H01L29/792 ,  H01L27/115

CPC classification number: H01L27/11573

Abstract: A semiconductor device includes a substrate, at least one logic device and a split gate memory device. The at least one logic device is located on the substrate. The split gate memory device is located on the substrate and comprises a memory gate and a select gate. The memory gate and the select gate are adjacent to and electrically isolated with each other. A top of the select gate is higher than a top of the memory gate.

Abstract translation: 半导体器件包括衬底，至少一个逻辑器件和分离栅极存储器件。 至少一个逻辑器件位于衬底上。 分离栅极存储器件位于衬底上并且包括存储器栅极和选择栅极。 存储器栅极和选择栅极彼此相邻并且电隔离。 选择栅极的顶部高于存储器栅极的顶部。

公开(公告)号：US10332882B2

公开(公告)日：2019-06-25

申请号：US14144356

申请日：2013-12-30

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Harry Hak-Lay Chuang ,  Wei-Cheng Wu

IPC: H01L27/092 ,  H01L21/28 ,  H01L27/11573 ,  H01L29/423 ,  H01L27/11531 ,  H01L27/06 ,  H01L27/108 ,  H01L27/11575 ,  H01L27/11568 ,  H01L29/792 ,  H01L27/11526 ,  H01L29/66 ,  H01L27/11521 ,  H01L27/105 ,  H01L23/525 ,  H01L21/8234

Abstract: A semiconductor device and a method for fabricating the semiconductor device are provided in the present disclosure. The semiconductor device includes a substrate including a first active region and a second active region divided by a shallow trench isolation (STI) region, a protective structure located on the STI region, a first semiconductor structure on the first active region, and a second semiconductor structure on the second active region of the substrate including a high-k dielectric layer and a metal gate layer over the high-k dielectric layer. The method for fabricating the semiconductor device is a process of the high-k dielectric layer deposited before the formation of the first and second semiconductor structures.

公开(公告)号：US10050050B2

公开(公告)日：2018-08-14

申请号：US14075817

申请日：2013-11-08

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Harry Hak-Lay Chuang ,  Wei-Cheng Wu ,  Ya-Chen Kao

IPC: H01L29/792 ,  H01L27/11568 ,  H01L29/66 ,  H01L27/11573 ,  H01L29/423 ,  H01L29/51 ,  H01L21/8238

Abstract: A semiconductor device includes a substrate, at least one split gate memory device, and at least one logic device. The split gate memory device is disposed on the substrate. The logic device is disposed on the substrate. A select gate or a main gate of the split gate memory device and a logic gate of the logic device are both made of metal, and the other gate of the split gate memory device is made of nonmetal.

公开(公告)号：US09202817B2

公开(公告)日：2015-12-01

申请号：US14161372

申请日：2014-01-22

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Harry Hak-Lay Chuang ,  Wei-Cheng Wu ,  Ya-Chen Kao

IPC: H01L21/336 ,  H01L27/115 ,  H01L29/423 ,  H01L21/28

CPC classification number: H01L27/1157 ,  H01L21/28282 ,  H01L27/11573 ,  H01L29/42332 ,  H01L29/4234 ,  H01L29/42344 ,  H01L29/66545 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/7881 ,  H01L29/792

Abstract: The present disclosure provides a semiconductor device and a method for manufacturing the same. The semiconductor device includes a substrate, at least one split gate memory device, and at least one logic device. The split gate memory device is disposed on the substrate. The logic device is disposed on the substrate. At least one of a select gate and a main gate of the split gate memory device and a logic gate of the logic device are made of metal. The method for manufacturing the semiconductor device includes forming at least one split gate stack and at least one logic gate stack and respectively replacing at least one of a dummy gate layer and a main gate layer in the split gate stack and the dummy gate layer in the logic gate stack with at least one metal memory gate and a metal logic gate.

Abstract translation: 本发明提供一种半导体器件及其制造方法。 半导体器件包括衬底，至少一个分离栅极存储器件和至少一个逻辑器件。 分离栅极存储器件设置在衬底上。 逻辑器件设置在衬底上。 分离栅极存储器件的选择栅极和主栅极中的至少一个以及逻辑器件的逻辑门由金属制成。 半导体器件的制造方法包括形成至少一个分离栅极堆叠和至少一个逻辑门极堆叠，并且分别替代分离栅极堆叠中的伪栅极层和主栅极层中的至少一个以及虚拟栅极层中的至少一个 具有至少一个金属存储器栅极和金属逻辑门的逻辑门极堆叠。

公开(公告)号：US10510763B2

公开(公告)日：2019-12-17

申请号：US15607337

申请日：2017-05-26

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chang-Ming Wu ,  Wei-Cheng Wu ,  Yuan-Tai Tseng ,  Shih-Chang Liu ,  Chia-Shiung Tsai ,  Ru-Liang Lee ,  Harry Hak-Lay Chuang

IPC: H01L27/11521 ,  H01L21/28 ,  H01L21/3213 ,  H01L21/02 ,  H01L21/311 ,  H01L21/3205 ,  H01L29/423 ,  H01L29/49 ,  H01L29/66 ,  H01L29/788 ,  H01L21/768 ,  H01L23/528 ,  H01L23/532

Abstract: A nonvolatile memory embedded in an advanced logic circuit and a method forming the same are provided. In the nonvolatile memory, the word lines and erase gates have top surfaces lower than the top surfaces of the control gate. In addition, the word lines and the erase gates are surrounded by dielectric material before a self-aligned silicidation process is performed. Therefore, no metal silicide can be formed on the word lines and the erase gate to produce problems of short circuit and current leakage in a later chemical mechanical polishing process.

公开(公告)号：US09673205B2

公开(公告)日：2017-06-06

申请号：US14834423

申请日：2015-08-24

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chang-Ming Wu ,  Wei-Cheng Wu ,  Yuan-Tai Tseng ,  Shih-Chang Liu ,  Chia-Shiung Tsai ,  Ru-Liang Lee ,  Harry Hak-Lay Chuang

IPC: H01L27/115 ,  H01L27/11521 ,  H01L21/02 ,  H01L21/28 ,  H01L21/311 ,  H01L21/3205 ,  H01L21/3213 ,  H01L29/423 ,  H01L29/49 ,  H01L29/66 ,  H01L29/788 ,  H01L21/768 ,  H01L23/528 ,  H01L23/532

CPC classification number: H01L27/11521 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/02532 ,  H01L21/02595 ,  H01L21/28273 ,  H01L21/31111 ,  H01L21/32055 ,  H01L21/32133 ,  H01L21/32137 ,  H01L21/768 ,  H01L23/528 ,  H01L23/53271 ,  H01L23/5329 ,  H01L29/42328 ,  H01L29/4238 ,  H01L29/4916 ,  H01L29/6656 ,  H01L29/66825 ,  H01L29/7883 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A nonvolatile memory embedded in an advanced logic circuit and a method forming the same are provided. In the nonvolatile memory, the word lines and erase gates have top surfaces lower than the top surfaces of the control gate. In addition, the word lines and the erase gates are surrounded by dielectric material before a self-aligned silicidation process is performed. Therefore, no metal silicide can be formed on the word lines and the erase gate to produce problems of short circuit and current leakage in a later chemical mechanical polishing process.

公开(公告)号：US20160056250A1

公开(公告)日：2016-02-25

申请号：US14481987

申请日：2014-09-10

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Harry Hak-Lay Chuang ,  Wei Cheng Wu ,  Shih-Chang Liu ,  Ya-Chen Kao

IPC: H01L29/423 ,  H01L29/66 ,  H01L29/792 ,  H01L27/115 ,  H01L27/105

CPC classification number: H01L29/42344 ,  H01L27/11573 ,  H01L29/665 ,  H01L29/6659 ,  H01L29/66833 ,  H01L29/7833 ,  H01L29/792

Abstract: Some embodiments of the present disclosure provide an integrated circuit (IC) for an embedded flash memory device. The IC includes a flash memory cell having a memory cell gate. A silicide contact pad is arranged in a recess of the memory cell gate. A top surface of the silicide contact pad is recessed relative to a top surface of the memory cell gate. Dielectric side-wall spacers extend along sidewalls of the recess from the top surface of the memory cell gate to the top surface of the silicide contact pad.

Abstract translation: 本公开的一些实施例提供了一种用于嵌入式闪存设备的集成电路（IC）。 IC包括具有存储单元门的闪存单元。 硅化物接触焊盘设置在存储单元栅极的凹部中。 硅化物接触焊盘的顶表面相对于存储单元栅极的顶表面凹陷。 电介质侧壁间隔物从凹槽的侧壁从存储单元栅极的顶表面延伸到硅化物接触焊盘的顶表面。

公开(公告)号：US09082630B2

公开(公告)日：2015-07-14

申请号：US14075617

申请日：2013-11-08

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Harry Hak-Lay Chuang ,  Wei-Cheng Wu

IPC: H01L29/00 ,  H01L27/06 ,  H01L21/8234 ,  H01L27/105

CPC classification number: H01L27/0617 ,  H01L21/823437 ,  H01L21/823456 ,  H01L21/823462 ,  H01L21/823828 ,  H01L21/82385 ,  H01L21/823857 ,  H01L27/088 ,  H01L27/092 ,  H01L27/1052

Abstract: A semiconductor device and a method for fabricating the semiconductor device are provided in the present disclosure. The semiconductor device includes a substrate including a first area and a second area divided by a shallow trench isolation (STI) area, a first dummy structure on the STI area, a second dummy structure located on the STI area, a first semiconductor structure on the first area, and a second semiconductor structure on the second area of the substrate including a high-k dielectric layer and a metal gate layer over the high-k dielectric layer. The method for fabricating the semiconductor device is a high-k dielectric first, high-k metal gate last procedure.

Abstract translation: 在本公开中提供半导体器件和制造半导体器件的方法。 该半导体器件包括：衬底，其包括第一区域和由浅沟槽隔离区域（STI）区域划分的第二区域; STI区域上的第一虚拟结构;位于STI区域上的第二虚拟结构;位于STI区域上的第一半导体结构; 第一区域和第二半导体结构，所述第二半导体结构在所述基板的所述第二区域上包括在所述高k电介质层上方的高k电介质层和金属栅极层。 制造半导体器件的方法是高k电介质第一，高k金属栅最后程序。

公开(公告)号：US09735245B2

公开(公告)日：2017-08-15

申请号：US14481987

申请日：2014-09-10

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Harry Hak-Lay Chuang ,  Wei Cheng Wu ,  Shih-Chang Liu ,  Ya-Chen Kao

IPC: H01L29/423 ,  H01L29/792 ,  H01L29/66 ,  H01L27/11573 ,  H01L29/78

CPC classification number: H01L29/42344 ,  H01L27/11573 ,  H01L29/665 ,  H01L29/6659 ,  H01L29/66833 ,  H01L29/7833 ,  H01L29/792

Abstract: Some embodiments of the present disclosure provide an integrated circuit (IC) for an embedded flash memory device. The IC includes a flash memory cell having a memory cell gate. A silicide contact pad is arranged in a recess of the memory cell gate. A top surface of the silicide contact pad is recessed relative to a top surface of the memory cell gate. Dielectric side-wall spacers extend along sidewalls of the recess from the top surface of the memory cell gate to the top surface of the silicide contact pad.

公开(公告)号：US09159842B1

公开(公告)日：2015-10-13

申请号：US14229191

申请日：2014-03-28

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chang-Ming Wu ,  Wei-Cheng Wu ,  Yuan-Tai Tseng ,  Shih-Chang Liu ,  Chia-Shiung Tsai ,  Ru-Liang Lee ,  Harry Hak-Lay Chuang

IPC: H01L29/02 ,  H01L29/788 ,  H01L29/49 ,  H01L29/423 ,  H01L21/28 ,  H01L29/66 ,  H01L21/3205 ,  H01L21/3213 ,  H01L21/311 ,  H01L21/02

CPC classification number: H01L27/11521 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/02532 ,  H01L21/02595 ,  H01L21/28273 ,  H01L21/31111 ,  H01L21/32055 ,  H01L21/32133 ,  H01L21/32137 ,  H01L21/768 ,  H01L23/528 ,  H01L23/53271 ,  H01L23/5329 ,  H01L29/42328 ,  H01L29/4238 ,  H01L29/4916 ,  H01L29/6656 ,  H01L29/66825 ,  H01L29/7883 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A nonvolatile memory embedded in an advanced logic circuit and a method forming the same are provided. In the nonvolatile memory, the word lines and erase gates have top surfaces lower than the top surfaces of the control gate. In addition, the word lines and the erase gates are surrounded by dielectric material before a self-aligned silicidation process is performed. Therefore, no metal silicide can be formed on the word lines and the erase gate to produce problems of short circuit and current leakage in a later chemical mechanical polishing process.

Abstract translation: 提供嵌入高级逻辑电路中的非易失性存储器及其形成方法。 在非易失性存储器中，字线和擦除栅极的顶表面比控制栅极的顶表面低。 此外，在进行自对准硅化处理之前，字线和擦除栅极被电介质材料包围。 因此，在后续的化学机械抛光工艺中，字线和擦除栅极上不会形成金属硅化物，从而产生短路和漏电的问题。