公开(公告)号：US12300593B2

公开(公告)日：2025-05-13

申请号：US18360169

申请日：2023-07-27

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chia-Ching Tsai ,  Yi-Wei Chiu ,  Hung Jui Chang ,  Li-Te Hsu

IPC: H01L21/768 ,  H01L23/498

Abstract: A dielectric layer is formed over a substrate, an anti-reflective layer is formed over the dielectric layer, and a first hardmask is formed over the anti-reflective layer. A via opening and a trench opening are formed within the dielectric layer using the anti-reflective layer and the first hardmask as masking materials. After the formation of the trench opening and the via opening, the first hardmask is removed. An interconnect is formed within the openings, and the interconnect has a via with a profile angle of between about 70° and about 80° and a depth ratio of between about 65% and about 70%.

公开(公告)号：US11430694B2

公开(公告)日：2022-08-30

申请号：US17087058

申请日：2020-11-02

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chia-Ching Tsai ,  Yi-Wei Chiu ,  Li-Te Hsu

IPC: H01L21/28 ,  H01L29/08 ,  H01L21/768 ,  H01L29/66 ,  H01L29/78 ,  H01L29/49 ,  H01L23/535 ,  H01L23/532 ,  H01L29/417 ,  H01L29/51

Abstract: A method includes forming a transistor, which includes forming a gate dielectric on a semiconductor region, forming a gate electrode over the gate dielectric, and forming a source/drain region extending into the semiconductor region. The method further includes forming a source/drain contact plug over and electrically coupling to the source/drain region, and forming a gate contact plug over and in contact with the gate electrode. At least one of the forming the gate electrode, the forming the source/drain contact plug, and the forming the gate contact plug includes forming a metal nitride barrier layer, and depositing a metal-containing layer over and in contact with the metal nitride barrier layer. The metal-containing layer includes at least one of a cobalt layer and a metal silicide layer.

公开(公告)号：US20210280464A1

公开(公告)日：2021-09-09

申请号：US17325608

申请日：2021-05-20

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chia-Ching Tsai ,  Yi-Wei Chiu ,  Li-Te Hsu

IPC: H01L21/768 ,  H01L29/66 ,  H01L21/28 ,  H01L29/78 ,  H01L29/08 ,  H01L29/49 ,  H01L23/535 ,  H01L23/532 ,  H01L29/417

Abstract: A method includes forming a transistor, which includes forming a gate dielectric on a semiconductor region, forming a gate electrode over the gate dielectric, and forming a source/drain region extending into the semiconductor region. The method further includes forming a source/drain contact plug over and electrically coupling to the source/drain region, and forming a gate contact plug over and in contact with the gate electrode. At least one of the forming the gate electrode, the forming the source/drain contact plug, and the forming the gate contact plug includes forming a metal nitride barrier layer, and depositing a metal-containing layer over and in contact with the metal nitride barrier layer. The metal-containing layer includes at least one of a cobalt layer and a metal silicide layer.

公开(公告)号：US20210257285A1

公开(公告)日：2021-08-19

申请号：US17306319

申请日：2021-05-03

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chia-Ching Tsai ,  Yi-Wei Chiu ,  Hung Jui Chang ,  Li-Te Hsu

IPC: H01L23/498 ,  H01L21/768

Abstract: A dielectric layer is formed over a substrate, an anti-reflective layer is formed over the dielectric layer, and a first hardmask is formed over the anti-reflective layer. A via opening and a trench opening are formed within the dielectric layer using the anti-reflective layer and the first hardmask as masking materials. After the formation of the trench opening and the via opening, the first hardmask is removed. An interconnect is formed within the openings, and the interconnect has a via with a profile angle of between about 70° and about 80° and a depth ratio of between about 65% and about 70%.

公开(公告)号：US11031279B2

公开(公告)日：2021-06-08

申请号：US15672123

申请日：2017-08-08

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chia-Kai Sun ,  Yi-Wei Chiu ,  Hung Jui Chang ,  Chia-Ching Tsai

IPC: H01L21/768 ,  H01L21/762 ,  H01L21/3065 ,  H01L21/308 ,  H01L29/423 ,  H01L21/28 ,  H01L29/51 ,  H01L21/311

Abstract: The present disclosure relates to a semiconductor device and a manufacturing method, and more particularly to a semiconductor device having reduced trench loading effect. The present disclosure provides a novel multi-layer cap film incorporating one or more oxygen-based layers for reducing trench loading effects in semiconductor devices. The multi-layer cap film can be made of a metal hard mask layer and one or more oxygen-based layers. The metal hard mask layer can be formed of titanium nitride (TiN). The oxygen-based layer can be formed of tetraethyl orthosilicate (TEOS).

公开(公告)号：US11996325B2

公开(公告)日：2024-05-28

申请号：US16942114

申请日：2020-07-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chia-Ching Tsai ,  Yi-Wei Chiu ,  Li-Te Hsu

IPC: H01L21/768

CPC classification number: H01L21/76832 ,  H01L21/76804 ,  H01L21/76807 ,  H01L21/76813 ,  H01L21/76834 ,  H01L21/76879

Abstract: A device includes a substrate, a first dielectric layer over the substrate, a first conductive feature in the first dielectric layer, and an etch stop layer over the first dielectric layer. The etch stop layer includes metal-doped aluminum nitride. The device further includes a second dielectric layer over the etch stop layer, and a second conductive feature in the second dielectric layer. The second conductive feature extends into the etch stop layer and contacts the first conductive feature.

公开(公告)号：US20240021473A1

公开(公告)日：2024-01-18

申请号：US18475753

申请日：2023-09-27

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chia-Ching Tsai ,  Yi-Wei Chiu ,  Li-Te Hsu

IPC: H01L21/768 ,  H01L29/66 ,  H01L21/28 ,  H01L29/78 ,  H01L29/08 ,  H01L29/49 ,  H01L23/535 ,  H01L23/532 ,  H01L29/417

CPC classification number: H01L21/76889 ,  H01L29/66795 ,  H01L29/66545 ,  H01L29/66636 ,  H01L21/28088 ,  H01L21/76805 ,  H01L21/76843 ,  H01L21/76895 ,  H01L21/7684 ,  H01L29/7851 ,  H01L29/0847 ,  H01L29/4966 ,  H01L23/535 ,  H01L23/53209 ,  H01L29/66553 ,  H01L29/41791 ,  H01L29/785 ,  H01L29/6656 ,  H01L29/665 ,  H01L29/513

Abstract: A method includes forming a transistor, which includes forming a gate dielectric on a semiconductor region, forming a gate electrode over the gate dielectric, and forming a source/drain region extending into the semiconductor region. The method further includes forming a source/drain contact plug over and electrically coupling to the source/drain region, and forming a gate contact plug over and in contact with the gate electrode. At least one of the forming the gate electrode, the forming the source/drain contact plug, and the forming the gate contact plug includes forming a metal nitride barrier layer, and depositing a metal-containing layer over and in contact with the metal nitride barrier layer. The metal-containing layer includes at least one of a cobalt layer and a metal silicide layer.

公开(公告)号：US11810819B2

公开(公告)日：2023-11-07

申请号：US17325608

申请日：2021-05-20

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chia-Ching Tsai ,  Yi-Wei Chiu ,  Li-Te Hsu

IPC: H01L29/66 ,  H01L21/28 ,  H01L21/768 ,  H01L29/78 ,  H01L29/08 ,  H01L29/49 ,  H01L23/535 ,  H01L23/532 ,  H01L29/417 ,  H01L29/51

CPC classification number: H01L21/76889 ,  H01L21/28088 ,  H01L21/7684 ,  H01L21/76805 ,  H01L21/76843 ,  H01L21/76895 ,  H01L23/535 ,  H01L23/53209 ,  H01L29/0847 ,  H01L29/41791 ,  H01L29/4966 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/66636 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/7851 ,  H01L29/513 ,  H01L29/517

Abstract: A method includes forming a transistor, which includes forming a gate dielectric on a semiconductor region, forming a gate electrode over the gate dielectric, and forming a source/drain region extending into the semiconductor region. The method further includes forming a source/drain contact plug over and electrically coupling to the source/drain region, and forming a gate contact plug over and in contact with the gate electrode. At least one of the forming the gate electrode, the forming the source/drain contact plug, and the forming the gate contact plug includes forming a metal nitride barrier layer, and depositing a metal-containing layer over and in contact with the metal nitride barrier layer. The metal-containing layer includes at least one of a cobalt layer and a metal silicide layer.

公开(公告)号：US10290547B2

公开(公告)日：2019-05-14

申请号：US15823134

申请日：2017-11-27

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chia-Ching Tsai ,  Yi-Wei Chiu ,  Li-Te Hsu

IPC: H01L21/8234 ,  H01L29/66 ,  H01L29/49 ,  H01L21/3213 ,  H01L21/321 ,  H01L21/311 ,  H01L29/78 ,  H01L27/088

Abstract: A method of manufacturing a semiconductor device includes forming a first layer of a conductive material in gate spaces created by removing portions of a dummy gate structure. The first layer further includes a top layer on an entire structure formed on a fin structure, and a gate space for a short channel gate and a gate space for a long channel gate. A first portion of the top layer is removed to leave a hard mask layer over a long channel gate region. The hard mask layer and a portion of heights of the conductive material in the gate spaces are removed to form a first structure. A second layer of the conductive material is formed over the first structure. Portions of the second layer are removed to create a recessed conductive portion for the short channel gate and a recessed conductive portion for the long channel gate.

公开(公告)号：US20240274467A1

公开(公告)日：2024-08-15

申请号：US18646870

申请日：2024-04-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chia-Ching Tsai ,  Yi-Wei Chiu ,  Li-Te Hsu

IPC: H01L21/768

CPC classification number: H01L21/76832 ,  H01L21/76804 ,  H01L21/76807 ,  H01L21/76813 ,  H01L21/76834 ,  H01L21/76879

Abstract: A device includes a substrate, a first dielectric layer over the substrate, a first conductive feature in the first dielectric layer, and an etch stop layer over the first dielectric layer. The etch stop layer includes metal-doped aluminum nitride. The device further includes a second dielectric layer over the etch stop layer, and a second conductive feature in the second dielectric layer. The second conductive feature extends into the etch stop layer and contacts the first conductive feature.