公开(公告)号：US20180204922A1

公开(公告)日：2018-07-19

申请号：US15918394

申请日：2018-03-12

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

发明人： Chung-Ting LI ,  Chih-Hao CHANG ,  Sheng-Yu CHANG ,  Jen-Hsiang LU ,  Jyun-Yang SHEN

IPC分类号： H01L29/417 ,  H01L29/78 ,  H01L29/06 ,  H01L29/66

CPC分类号： H01L29/41791 ,  H01L21/823821 ,  H01L21/845 ,  H01L27/1104 ,  H01L29/0649 ,  H01L29/66795 ,  H01L29/7848 ,  H01L29/785

摘要： In a method of manufacturing a semiconductor device, a first fin structure for an n-channel fin field effect transistor (FinFET) is formed over a substrate. An isolation insulating layer is formed over the substrate such that an upper portion of the first fin structure protrudes from the isolation insulating layer. A gate structure is formed over a part of the upper portion of the first fin structure. A first source/drain (S/D) epitaxial layer is formed over the first fin structure not covered by the gate structure. A cap epitaxial layer is formed over the first S/D epitaxial layer. The first S/D epitaxial layer includes SiP, and the cap epitaxial layer includes SiC with a carbon concentration is in a range from 0.5 atomic % to 5 atomic %.

公开(公告)号：US20190229197A1

公开(公告)日：2019-07-25

申请号：US16368840

申请日：2019-03-28

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

发明人： Chung-Ting LI ,  Chih-Hao CHANG ,  Sheng-Yu CHANG ,  Jen-Hsiang LU ,  Jyun-Yang SHEN

IPC分类号： H01L29/417 ,  H01L29/78 ,  H01L29/66 ,  H01L27/11 ,  H01L29/06 ,  H01L21/84 ,  H01L21/8238

摘要： In a method of manufacturing a semiconductor device, a first fin structure for an n-channel fin field effect transistor (FinFET) is formed over a substrate. An isolation insulating layer is formed over the substrate such that an upper portion of the first fin structure protrudes from the isolation insulating layer. A gate structure is formed over a part of the upper portion of the first fin structure. A first source/drain (S/D) epitaxial layer is formed over the first fin structure not covered by the gate structure. A cap epitaxial layer is formed over the first S/D epitaxial layer. The first S/D epitaxial layer includes SiP, and the cap epitaxial layer includes SiC with a carbon concentration is in a range from 0.5 atomic % to 5 atomic %.

公开(公告)号：US20180138280A1

公开(公告)日：2018-05-17

申请号：US15353922

申请日：2016-11-17

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

发明人： Chung-Ting Li ,  Jen-Hsiang LU ,  Chih-Hao CHANG

IPC分类号： H01L29/417 ,  H01L29/66 ,  H01L23/522 ,  H01L21/28 ,  H01L23/532 ,  H01L21/768

摘要： A semiconductor device includes a semiconductor substrate, at least one gate stack, a gate spacer and a dielectric cap. The gate stack is located on the semiconductor substrate. The gate spacer is located on a sidewall of the gate stack. The gate spacer includes a first dielectric layer and a second dielectric layer with different etch properties. The dielectric cap at least caps the gate spacer. The dielectric cap and the second dielectric layer define a gap therebetween.

公开(公告)号：US20200303511A1

公开(公告)日：2020-09-24

申请号：US16889245

申请日：2020-06-01

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Tsung-Han TSAI ,  Jen-Hsiang LU ,  Shih-Hsun CHANG

IPC分类号： H01L29/423 ,  H01L29/786 ,  H01L29/66 ,  H01L29/40 ,  H01L21/02 ,  H01L29/78

摘要： A semiconductor device structure is provided. The semiconductor device structure includes a fin structure formed over a semiconductor substrate and a gate structure formed across the fin structure. The semiconductor device structure also includes an isolation feature over a semiconductor substrate and below a portion of the gate structure and two spacer elements respectively formed over a first sidewall and a second sidewall of the gate structure. In addition, the first sidewall is opposite to the second sidewall and the two spacer elements have hydrophobic surfaces respectively facing the first sidewall and the second sidewall, and the gate structure includes a gate dielectric layer and a gate electrode layer separating the gate dielectric layer from the hydrophobic surfaces of the two spacer elements.

公开(公告)号：US20200035800A1

公开(公告)日：2020-01-30

申请号：US16048833

申请日：2018-07-30

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Tsung-Han TSAI ,  Jen-Hsiang LU ,  Shih-Hsun CHANG

IPC分类号： H01L29/423 ,  H01L29/786 ,  H01L29/78 ,  H01L29/40 ,  H01L21/02 ,  H01L29/66

摘要： A method of forming a semiconductor device structure is provided. The method includes forming an isolation feature over a semiconductor substrate. The semiconductor substrate includes a fin structure over the isolation feature. Two opposing spacer elements are formed over the isolation feature and across the fin structure so as to define a gate opening. The gate opening exposes the fin structure and the isolation feature and inner sidewalls of the gate opening have carbon-containing hydrophobic surfaces. A gate structure is formed in the gate opening with the carbon-containing hydrophobic surfaces.

公开(公告)号：US20210280516A1

公开(公告)日：2021-09-09

申请号：US17330834

申请日：2021-05-26

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

发明人： Hung-Ming CHEN ,  Yu-Chang LIN ,  Chung-Ting LI ,  Jen-Hsiang LU ,  Hou-Ju LI ,  Chih-Pin TSAO

IPC分类号： H01L23/535 ,  H01L29/66 ,  H01L29/78 ,  H01L21/768 ,  H01L29/417

摘要： A method includes forming a gate structure on a substrate; forming a gate spacer on a sidewall of the gate structure; forming a carbon-containing layer on the gate spacer; diffusing carbon from the carbon-containing layer into a portion of the substrate below the gate spacer; forming a recess in the substrate on one side of the gate spacer opposite to the gate structure; and forming an epitaxy feature in the recess of the substrate.

公开(公告)号：US20170243944A1

公开(公告)日：2017-08-24

申请号：US15098060

申请日：2016-04-13

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

发明人： Chung-Ting LI ,  Chih-Hao CHANG ,  Sheng-Yu CHANG ,  Jen-Hsiang LU ,  Jyun-Yang SHEN

IPC分类号： H01L29/417 ,  H01L29/66 ,  H01L29/06 ,  H01L29/78

CPC分类号： H01L29/41791 ,  H01L21/823821 ,  H01L21/845 ,  H01L27/1104 ,  H01L29/0649 ,  H01L29/66795 ,  H01L29/7848 ,  H01L29/785

摘要： In a method of manufacturing a semiconductor device, a first fin structure for an n-channel fin field effect transistor (FinFET) is formed over a substrate. An isolation insulating layer is formed over the substrate such that an upper portion of the first fin structure protrudes from the isolation insulating layer. A gate structure is formed over a part of the upper portion of the first fin structure. A first source/drain (S/D) epitaxial layer is formed over the first fin structure not covered by the gate structure. A cap epitaxial layer is formed over the first S/D epitaxial layer. The first S/D epitaxial layer includes SiP, and the cap epitaxial layer includes SiC with a carbon concentration is in a range from 0.5 atomic % to 5 atomic %.

公开(公告)号：US20160359043A1

公开(公告)日：2016-12-08

申请号：US14730210

申请日：2015-06-03

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

发明人： Yi-Jen CHEN ,  CHIA-CHUN Liao ,  Chun-Sheng LIANG ,  Shih-Hsun CHANG ,  Jen-Hsiang LU

IPC分类号： H01L29/78 ,  H01L21/02 ,  H01L29/165 ,  H01L29/66 ,  H01L29/06

CPC分类号： H01L29/7851 ,  H01L21/02532 ,  H01L21/0262 ,  H01L29/165 ,  H01L29/66545 ,  H01L29/66818 ,  H01L29/7848 ,  H01L29/7849

摘要： A method of manufacturing a semiconductor Fin FET includes forming a fin structure over a substrate. The fin structure includes an upper layer, part of which is exposed from an isolation insulating layer. A dummy gate structure is formed over part of the fin structure. The dummy gate structure includes a dummy gate electrode layer and a dummy gate dielectric layer. A source and a drain are formed. The dummy gate electrode is removed so that the upper layer covered by the dummy gate dielectric layer is exposed. The upper layer of the fin structure is removed to make a recess formed by the dummy gate dielectric layer. Part of the upper layer remains at a bottom of the recess. A channel layer is formed in the recess. The dummy gate dielectric layer is removed. A gate structure is formed over the channel layer.

摘要翻译： 制造半导体Fin FET的方法包括在衬底上形成翅片结构。 翅片结构包括上层，其一部分从隔离绝缘层露出。 在鳍部结构的一部分上形成虚拟栅极结构。 虚拟栅极结构包括伪栅极电极层和伪栅极电介质层。 形成源极和漏极。 去除虚拟栅极电极，使得由虚拟栅极介电层覆盖的上层被暴露。 去除翅片结构的上层以形成由虚拟栅极电介质层形成的凹部。 上层的一部分保留在凹部的底部。 在凹部中形成沟道层。 去除虚拟栅介质层。 在沟道层上形成栅极结构。