公开(公告)号：US20170207095A1

公开(公告)日：2017-07-20

申请号：US14996031

申请日：2016-01-14

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Kai-Hsuan LEE ,  Jyh-Cherng SHEU ,  Sung-Li WANG ,  Cheng-Yu YANG ,  Sheng-Chen WANG ,  Sai-Hooi YEONG

IPC: H01L21/285 ,  H01L29/08 ,  H01L29/78 ,  H01L29/06 ,  H01L29/66 ,  H01L21/768

CPC classification number: H01L21/28518 ,  H01L21/76843 ,  H01L21/76855 ,  H01L23/485 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/41791 ,  H01L29/66545 ,  H01L29/66795

Abstract: In a method of manufacturing a semiconductor device, a first layer containing an amorphous first material is formed by a deposition process over a semiconductor layer. A second layer containing a metal second material is formed over the first layer. A thermal process is performed to form an alloy layer of the amorphous first material and the metal second material.

公开(公告)号：US20180033687A1

公开(公告)日：2018-02-01

申请号：US15223902

申请日：2016-07-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Min-Hsiu HUNG ,  Sung-Li WANG ,  Pei-Wen WU ,  Yida LI ,  Chih-Wei CHANG ,  Huang-Yi HUANG ,  Cheng-Tung LIN ,  Jyh-Cherng SHEU ,  Yee-Chia YEO ,  Chi-On CHUI

IPC: H01L21/768

CPC classification number: H01L21/76856 ,  H01L21/28518 ,  H01L21/76843 ,  H01L21/76855 ,  H01L23/485 ,  H01L23/5226 ,  H01L23/53209 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53252 ,  H01L23/53266

Abstract: Structures and formation methods of a semiconductor device structure are provided. The method includes forming a dielectric layer over a semiconductor substrate and forming an opening in the dielectric layer to expose a conductive element. The method also includes forming a conductive layer over the conductive element and modifying an upper portion of the conductive layer using a plasma operation to form a modified region. The method further includes forming a conductive plug over the modified region.

公开(公告)号：US20210035806A1

公开(公告)日：2021-02-04

申请号：US17074110

申请日：2020-10-19

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Kai-Hsuan LEE ,  Jyh-Cherng SHEU ,  Sung-Li WANG ,  Cheng-Yu YANG ,  Sheng-Chen WANG ,  Sai-Hooi YEONG

IPC: H01L21/285 ,  H01L29/66 ,  H01L29/06 ,  H01L29/08 ,  H01L29/417 ,  H01L21/768

Abstract: In a method of manufacturing a semiconductor device, a first layer containing an amorphous first material is formed by a deposition process over a semiconductor layer. A second layer containing a metal second material is formed over the first layer. A thermal process is performed to form an alloy layer of the amorphous first material and the metal second material.

公开(公告)号：US20190123161A1

公开(公告)日：2019-04-25

申请号：US16228872

申请日：2018-12-21

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Yee-Chia YEO ,  Sung-Li WANG ,  Chi On CHUI ,  Jyh-Cherng SHEU ,  Hung-Li CHIANG ,  I-Sheng CHEN

IPC: H01L29/45 ,  H01L27/092 ,  H01L27/088 ,  H01L21/8234 ,  H01L29/417 ,  H01L29/08 ,  H01L21/8238 ,  H01L29/78 ,  H01L23/522

CPC classification number: H01L29/45 ,  H01L21/823425 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823821 ,  H01L23/5226 ,  H01L27/0886 ,  H01L27/092 ,  H01L27/0924 ,  H01L29/0847 ,  H01L29/41791 ,  H01L29/456 ,  H01L29/7851 ,  H01L2029/7858

Abstract: A semiconductor device includes a field effect transistor (FET). The FET includes a first channel, a first source and a first drain; a second channel, a second source and a second drain; and a gate structure disposed over the first and second channels. The gate structure includes a gate dielectric layer and a gate electrode layer. The first source includes a first crystal semiconductor layer and the second source includes a second crystal semiconductor layer. The first source and the second source are connected by an alloy layer made of one or more Group IV element and one or more transition metal elements. The first crystal semiconductor layer is not in direct contact with the second crystal semiconductor layer.

公开(公告)号：US20230067088A1

公开(公告)日：2023-03-02

申请号：US17461672

申请日：2021-08-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Han-De CHEN ,  Yun-Chen TENG ,  Chen-Fong TSAI ,  Jyh-Cherng SHEU ,  Huicheng CHANG ,  Yee-Chia YEO

IPC: H01L23/00 ,  H01L21/66 ,  H01L21/67 ,  H01L21/02 ,  B23K1/00

Abstract: The present disclosure provides a substrate bonding apparatus capable of temperature monitoring and temperature control. The substrate bonding apparatus comprises a fluid cooling module and a sensor module for detecting temperatures at multiple zones (e.g., two or more zones) within a substrate. The substrate bonding apparatus according to the present disclosure achieves temperature stabilization within the substrate. The substrate bonding apparatus further improves bonding process performance by reducing distortion residual, reducing bubbles on edges of the substrate, and reducing non-bonded area within the substrate.

公开(公告)号：US20200212191A1

公开(公告)日：2020-07-02

申请号：US16814154

申请日：2020-03-10

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Yee-Chia YEO ,  Sung-Li WANG ,  Chi On CHUI ,  Jyh-Cherng SHEU ,  Hung-Li CHIANG ,  I-Sheng CHEN

IPC: H01L29/45 ,  H01L21/8238 ,  H01L27/092 ,  H01L21/8234 ,  H01L23/522 ,  H01L27/088 ,  H01L29/08 ,  H01L29/417 ,  H01L29/78

Abstract: A semiconductor device includes a field effect transistor (FET). The FET includes a first channel, a first source and a first drain; a second channel, a second source and a second drain; and a gate structure disposed over the first and second channels. The gate structure includes a gate dielectric layer and a gate electrode layer. The first source includes a first crystal semiconductor layer and the second source includes a second crystal semiconductor layer. The first source and the second source are connected by an alloy layer made of one or more Group IV element and one or more transition metal elements. The first crystal semiconductor layer is not in direct contact with the second crystal semiconductor layer.

公开(公告)号：US20180151683A1

公开(公告)日：2018-05-31

申请号：US15418995

申请日：2017-01-30

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Yee-Chia YEO ,  Hung-Li CHIANG ,  Jyh-Cherng SHEU ,  Sung-Li WANG ,  I-Sheng CHEN ,  Chi On CHUI

IPC: H01L29/45 ,  H01L27/088 ,  H01L27/092 ,  H01L29/78 ,  H01L29/08 ,  H01L23/522 ,  H01L21/8234 ,  H01L29/417

CPC classification number: H01L29/45 ,  H01L21/823425 ,  H01L21/823807 ,  H01L21/823814 ,  H01L23/5226 ,  H01L27/0886 ,  H01L27/092 ,  H01L27/0924 ,  H01L29/0847 ,  H01L29/41791 ,  H01L29/456 ,  H01L29/7851 ,  H01L2029/7858

Abstract: A semiconductor device includes a field effect transistor (FET). The FET includes a first channel, a first source and a first drain; a second channel, a second source and a second drain; and a gate structure disposed over the first and second channels. The gate structure includes a gate dielectric layer and a gate electrode layer. The first source includes a first crystal semiconductor layer and the second source includes a second crystal semiconductor layer. The first source and the second source are connected by an alloy layer made of one or more Group IV element and one or more transition metal elements. The first crystal semiconductor layer is not in direct contact with the second crystal semiconductor layer.

公开(公告)号：US20180102436A1

公开(公告)日：2018-04-12

申请号：US15837826

申请日：2017-12-11

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Hung-Li CHIANG ,  Cheng-Yi PENG ,  Jyh-Cherng SHEU ,  Yee-Chia YEO

IPC: H01L29/78 ,  H01L29/06 ,  H01L23/535 ,  H01L29/417 ,  H01L29/66

CPC classification number: H01L29/7849 ,  H01L21/26513 ,  H01L21/26586 ,  H01L23/535 ,  H01L29/0649 ,  H01L29/41791 ,  H01L29/66795 ,  H01L29/66803 ,  H01L29/7848 ,  H01L29/785 ,  H01L2029/7858

Abstract: A semiconductor device includes a substrate, a fin structure disposed over the substrate and including a channel region and a source/drain region, a gate structure disposed over at least a portion of the fin structure, the channel region being beneath the gate structure and the source/drain region being outside of the gate structure, a strain material layer disposed over the source/drain region, the strain material layer providing stress to the first channel region, and a contact layer wrapping around the first strain material layer. A width of the source/drain region is smaller than a width of the channel region.

公开(公告)号：US20170069756A1

公开(公告)日：2017-03-09

申请号：US15280216

申请日：2016-09-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hung-Li CHIANG ,  Cheng-Yi PENG ,  Jyh-Cherng SHEU ,  Yee-Chia YEO

IPC: H01L29/78 ,  H01L23/535 ,  H01L29/06 ,  H01L29/417

CPC classification number: H01L29/7849 ,  H01L21/26513 ,  H01L21/26586 ,  H01L23/535 ,  H01L29/0649 ,  H01L29/41791 ,  H01L29/66795 ,  H01L29/66803 ,  H01L29/7848 ,  H01L29/785 ,  H01L2029/7858

Abstract: A semiconductor device includes a substrate, a fin structure disposed over the substrate and including a channel region and a source/drain region, a gate structure disposed over at least a portion of the fin structure, the channel region being beneath the gate structure and the source/drain region being outside of the gate structure, a strain material layer disposed over the source/drain region, the strain material layer providing stress to the first channel region, and a contact layer wrapping around the first strain material layer. A width of the source/drain region is smaller than a width of the channel region.

Abstract translation: 半导体器件包括衬底，鳍状结构，设置在衬底上并且包括沟道区和源极/漏极区，栅极结构设置在鳍结构的至少一部分上，沟道区位于栅极结构之下， 源极/漏极区域在栅极结构外部，应变材料层设置在源极/漏极区域上，应变材料层向第一沟道区域提供应力，以及围绕第一应变材料层缠绕的接触层。 源极/漏极区域的宽度小于沟道区域的宽度。