公开(公告)号：US11004691B2

公开(公告)日：2021-05-11

申请号：US16714600

申请日：2019-12-13

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chen-Hao Wu ,  Shen-Nan Lee ,  Chung-Wei Hsu ,  Tsung-Ling Tsai ,  Teng-Chun Tsai

IPC: H01L21/321 ,  H01L21/3105 ,  H01L21/768 ,  H01L29/417 ,  H01L29/66 ,  H01L29/165 ,  H01L29/78 ,  H01L29/08

Abstract: A method includes: forming source/drain epitaxy structures over a semiconductor fin; forming a first ILD layer covering the source/drain epitaxy structures; forming a gate structure over the semiconductor fin and between the source/drain epitaxy structures; forming a capping layer over the gate structure; thinning the capping layer; forming a hard mask layer over the capping layer; forming a second ILD layer spanning the hard mask layer and the first ILD layer; forming, by using an etching operation, a contact hole passing through the first and second ILD layers to one of the source/drain epitaxy structures, the etching operation being performed such that the hard mask layer has a notched corner in the contact hole; filling the contact hole with a conductive material; and performing a CMP process on the conductive material until that the notched corner of the hard mask layer is removed.

公开(公告)号：US10510555B2

公开(公告)日：2019-12-17

申请号：US16053981

申请日：2018-08-03

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chen-Hao Wu ,  Shen-Nan Lee ,  Chung-Wei Hsu ,  Tsung-Ling Tsai ,  Teng-Chun Tsai

IPC: H01L21/321 ,  H01L21/768 ,  H01L29/417 ,  H01L29/66 ,  H01L29/165 ,  H01L29/78 ,  H01L21/3105 ,  H01L29/08

Abstract: A method for manufacturing a semiconductor device includes forming a gate electrode over a substrate; forming a hard mask over the gate electrode, in which the hard mask comprises a metal oxide; forming an interlayer dielectric (ILD) layer over the hard mask; forming a contact hole in the ILD layer, wherein the contact hole exposes a source/drain; filling the contact hole with a conductive material; and applying a chemical mechanical polish process to the ILD layer and the conductive material, wherein the chemical mechanical polish process stops at the hard mask, the chemical mechanical polish process uses a slurry containing a boric acid or its derivative, the chemical mechanical polish process has a first removal rate of the ILD layer and a second removal rate of the hard mask, and a first ratio of the first removal rate to the second removal rate is greater than about 5.

公开(公告)号：US11120995B2

公开(公告)日：2021-09-14

申请号：US16700889

申请日：2019-12-02

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chung-Wei Hsu ,  Yu-Chung Su ,  Chen-Hao Wu ,  Shen-Nan Lee ,  Tsung-Ling Tsai ,  Teng-Chun Tsai

IPC: H01L21/308 ,  H01L21/306 ,  H01L29/66 ,  H01L21/311 ,  H01L21/8234 ,  H01L29/78 ,  H01L21/3105

Abstract: A method includes forming a bottom layer of a multi-layer mask over a first gate structure extending across a fin; performing a chemical treatment to treat an upper portion of the bottom layer of the multi-layer mask, while leaving a lower portion of the bottom layer of the multi-layer mask untreated; forming a sacrificial layer over the bottom layer of the multi-layer mask; performing a polish process on the sacrificial layer, in which the treated upper portion of the bottom layer of the multi-layer mask has a slower removal rate in the polish process than that of the untreated lower portion of the bottom layer of the multi-layer mask; forming middle and top layers of the multi-layer mask; patterning the multi-layer mask; and etching an exposed portion of the first gate structure to break the first gate structure into a plurality of second gate structures.

公开(公告)号：US20210257302A1

公开(公告)日：2021-08-19

申请号：US17313558

申请日：2021-05-06

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Tsung-Ling Tsai ,  Shen-Nan Lee ,  Mrunal A. Khaderbad ,  Chung-Wei Hsu ,  Chen-Hao Wu ,  Teng-Chun Tsai

IPC: H01L23/535 ,  H01L23/522 ,  H01L23/528 ,  H01L23/532 ,  H01L21/768

Abstract: Partial barrier-free vias and methods for forming such are disclosed herein. An exemplary interconnect structure of a multilayer interconnect feature includes a dielectric layer. A cobalt-comprising interconnect feature and a partial barrier-free via are disposed in the dielectric layer. The partial barrier-free via includes a first via plug portion disposed on and physically contacting the cobalt-comprising interconnect feature and the dielectric layer, a second via plug portion disposed over the first via plug portion, and a via barrier layer disposed between the second via plug portion and the first via plug portion. The via barrier layer is further disposed between the second via plug portion and the dielectric layer. The cobalt-comprising interconnect feature can be a device-level contact or a conductive line of the multilayer interconnect feature. The first via plug portion and the second via plug portion can include tungsten, cobalt, and/or ruthenium.

公开(公告)号：US10269579B1

公开(公告)日：2019-04-23

申请号：US15907030

申请日：2018-02-27

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Shen-Nan Lee ,  Teng-Chun Tsai ,  Chung-Wei Hsu ,  Chen-Hao Wu ,  Tsung-Ling Tsai

IPC: H01L21/302 ,  H01L21/321 ,  C09G1/02 ,  H01L21/306 ,  H01L21/768

Abstract: A method of manufacturing a semiconductor device includes providing a substrate including a silicon oxide layer and a metal oxide layer covering the silicon oxide layer. A CMP slurry is prepared. The CMP slurry includes plural abrasive particles bearing negative charges, a Lewis base including a (XaYb)− group, and a buffer solution. The X represents a IIIA group element or an early transitional metal, and Y represents a pnictogen element, a chalcogen element or a halogen element. The CMP slurry has a pH in a range substantially from 2 to 7. Next, a planarization operation is performed on a surface of the metal oxide layer until a surface of the silicon oxide layer exposed. The planarization operation has a high polishing selectivity of the metal oxide layer with respect to the silicon oxide layer.

公开(公告)号：US20200006230A1

公开(公告)日：2020-01-02

申请号：US16399697

申请日：2019-04-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Tsung-Ling Tsai ,  Shen-Nan Lee ,  Mrunal A. Khaderbad ,  Chung-Wei Hsu ,  Chen-Hao Wu ,  Teng-Chun Tsai

IPC: H01L23/535 ,  H01L23/522 ,  H01L23/528 ,  H01L23/532 ,  H01L21/768

Abstract: Partial barrier-free vias and methods for forming such are disclosed herein. An exemplary interconnect structure of a multilayer interconnect feature includes a dielectric layer. A cobalt-comprising interconnect feature and a partial barrier-free via are disposed in the dielectric layer. The partial barrier-free via includes a first via plug portion disposed on and physically contacting the cobalt-comprising interconnect feature and the dielectric layer, a second via plug portion disposed over the first via plug portion, and a via barrier layer disposed between the second via plug portion and the first via plug portion. The via barrier layer is further disposed between the second via plug portion and the dielectric layer. The cobalt-comprising interconnect feature can be a device-level contact or a conductive line of the multilayer interconnect feature. The first via plug portion and the second via plug portion can include tungsten, cobalt, and/or ruthenium.

公开(公告)号：US20230361042A1

公开(公告)日：2023-11-09

申请号：US18357500

申请日：2023-07-24

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Tsung-Ling Tsai ,  Shen-Nan Lee ,  Mrunal A. Khaderbad ,  Chung-Wei Hsu ,  Chen-Hao Wu ,  Teng-Chun Tsai

IPC: H01L23/535 ,  H01L23/522 ,  H01L23/528 ,  H01L23/532 ,  H01L21/768

CPC classification number: H01L23/535 ,  H01L21/76805 ,  H01L21/76816 ,  H01L21/7684 ,  H01L21/76847 ,  H01L21/76879 ,  H01L21/76895 ,  H01L23/5226 ,  H01L23/5283 ,  H01L23/53209 ,  H01L23/53252 ,  H01L23/53266

Abstract: Partial barrier-free vias and methods for forming such are disclosed herein. An exemplary interconnect structure of a multilayer interconnect feature includes a dielectric layer. A cobalt-comprising interconnect feature and a partial barrier-free via are disposed in the dielectric layer. The partial barrier-free via includes a first via plug portion disposed on and physically contacting the cobalt-comprising interconnect feature and the dielectric layer, a second via plug portion disposed over the first via plug portion, and a via barrier layer disposed between the second via plug portion and the first via plug portion. The via barrier layer is further disposed between the second via plug portion and the dielectric layer. The cobalt-comprising interconnect feature can be a device-level contact or a conductive line of the multilayer interconnect feature. The first via plug portion and the second via plug portion can include tungsten, cobalt, and/or ruthenium.

公开(公告)号：US11776910B2

公开(公告)日：2023-10-03

申请号：US17313558

申请日：2021-05-06

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Tsung-Ling Tsai ,  Shen-Nan Lee ,  Mrunal A. Khaderbad ,  Chung-Wei Hsu ,  Chen-Hao Wu ,  Teng-Chun Tsai

IPC: H01L23/535 ,  H01L23/528 ,  H01L23/522 ,  H01L23/532 ,  H01L21/768

CPC classification number: H01L23/535 ,  H01L21/7684 ,  H01L21/76805 ,  H01L21/76816 ,  H01L21/76847 ,  H01L21/76879 ,  H01L21/76895 ,  H01L23/5226 ,  H01L23/5283 ,  H01L23/53209 ,  H01L23/53252 ,  H01L23/53266

Abstract: Partial barrier-free vias and methods for forming such are disclosed herein. An exemplary interconnect structure of a multilayer interconnect feature includes a dielectric layer. A cobalt-comprising interconnect feature and a partial barrier-free via are disposed in the dielectric layer. The partial barrier-free via includes a first via plug portion disposed on and physically contacting the cobalt-comprising interconnect feature and the dielectric layer, a second via plug portion disposed over the first via plug portion, and a via barrier layer disposed between the second via plug portion and the first via plug portion. The via barrier layer is further disposed between the second via plug portion and the dielectric layer. The cobalt-comprising interconnect feature can be a device-level contact or a conductive line of the multilayer interconnect feature. The first via plug portion and the second via plug portion can include tungsten, cobalt, and/or ruthenium.

公开(公告)号：US11756825B2

公开(公告)日：2023-09-12

申请号：US16953949

申请日：2020-11-20

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Shen-Nan Lee ,  Teng-Chun Tsai ,  Chen-Hao Wu ,  Chu-An Lee ,  Chun-Hung Liao ,  Tsung-Ling Tsai

IPC: H01L21/768 ,  H01L23/532 ,  H01L23/522

CPC classification number: H01L21/76802 ,  H01L21/7684 ,  H01L21/76831 ,  H01L21/76879 ,  H01L23/5226 ,  H01L23/53209

Abstract: A semiconductor structure is provided, including a conductive layer, a dielectric layer over the conductive layer, a ruthenium material in the dielectric layer and in contact with a portion of the conductive layer, and a ruthenium oxide material in the dielectric layer laterally between the ruthenium material and the dielectric layer.

公开(公告)号：US11004794B2

公开(公告)日：2021-05-11

申请号：US16399697

申请日：2019-04-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Tsung-Ling Tsai ,  Shen-Nan Lee ,  Mrunal A. Khaderbad ,  Chung-Wei Hsu ,  Chen-Hao Wu ,  Teng-Chun Tsai

IPC: H01L23/535 ,  H01L23/522 ,  H01L23/528 ,  H01L23/532 ,  H01L21/768

Abstract: Partial barrier-free vias and methods for forming such are disclosed herein. An exemplary interconnect structure of a multilayer interconnect feature includes a dielectric layer. A cobalt-comprising interconnect feature and a partial barrier-free via are disposed in the dielectric layer. The partial barrier-free via includes a first via plug portion disposed on and physically contacting the cobalt-comprising interconnect feature and the dielectric layer, a second via plug portion disposed over the first via plug portion, and a via barrier layer disposed between the second via plug portion and the first via plug portion. The via barrier layer is further disposed between the second via plug portion and the dielectric layer. The cobalt-comprising interconnect feature can be a device-level contact or a conductive line of the multilayer interconnect feature. The first via plug portion and the second via plug portion can include tungsten, cobalt, and/or ruthenium.