公开(公告)号：US11527543B2

公开(公告)日：2022-12-13

申请号：US16916959

申请日：2020-06-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yen-Jou Wu ,  Chih-Ming Lee ,  Keng-Ying Liao ,  Ping-Pang Hsieh ,  Su-Yu Yeh ,  Hsin-Hui Lin ,  Yu-Liang Wang

IPC: H01L27/11524 ,  H01L27/11519 ,  H01L29/788 ,  H01L29/423 ,  H01L29/66 ,  G11C8/14

Abstract: The present disclosure describes a patterning process for a strap region in a memory cell for the removal of material between polysilicon lines. The patterning process includes depositing a first hard mask layer in a divot formed on a top portion of a polysilicon layer interposed between a first polysilicon gate structure and a second polysilicon gate; depositing a second hard mask layer on the first hard mask layer. The patterning process also includes performing a first etch to remove the second hard mask layer and a portion of the second hard mask layer from the divot, performing a second etch to remove the second hard mask layer from the divot; and performing a third etch to remove the polysilicon layer not covered by the first and second hard mask layers to form a separation between the first polysilicon gate structure and the second polysilicon structure.

公开(公告)号：US20240363791A1

公开(公告)日：2024-10-31

申请号：US18766336

申请日：2024-07-08

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih Wei Sung ,  Chung-Bin Tseng ,  Keng-Ying Liao ,  Yen-Jou Wu ,  Po-Zen Chen ,  Su-Yu Yeh ,  Ching-Chung Su

IPC: H01L31/18 ,  H01L23/544 ,  H01L27/146

CPC classification number: H01L31/1876 ,  H01L23/544 ,  H01L27/14621 ,  H01L27/14627 ,  H01L27/14636 ,  H01L27/1464 ,  H01L27/14683 ,  H01L27/14687 ,  H01L31/186 ,  H01L31/1888 ,  H01L2223/54426

Abstract: A method includes forming image sensors in a semiconductor substrate. A first alignment mark is formed close to a front side of the semiconductor substrate. The method further includes performing a backside polishing process to thin the semiconductor substrate, forming a second alignment mark on the backside of the semiconductor substrate, and forming a feature on the backside of the semiconductor substrate. The feature is formed using the second alignment mark for alignment.

公开(公告)号：US20220359781A1

公开(公告)日：2022-11-10

申请号：US17814726

申请日：2022-07-25

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih Wei Sung ,  Chung-Bin Tseng ,  Keng-Ying Liao ,  Yen-Jou Wu ,  Po-Zen Chen ,  Su-Yu Yeh ,  Ching-Chung Su

IPC: H01L31/18 ,  H01L27/146 ,  H01L23/544

Abstract: A method includes forming image sensors in a semiconductor substrate. A first alignment mark is formed close to a front side of the semiconductor substrate. The method further includes performing a backside polishing process to thin the semiconductor substrate, forming a second alignment mark on the backside of the semiconductor substrate, and forming a feature on the backside of the semiconductor substrate. The feature is formed using the second alignment mark for alignment.

公开(公告)号：US12094997B2

公开(公告)日：2024-09-17

申请号：US17814726

申请日：2022-07-25

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih Wei Sung ,  Chung-Bin Tseng ,  Keng-Ying Liao ,  Yen-Jou Wu ,  Po-Zen Chen ,  Su-Yu Yeh ,  Ching-Chung Su

IPC: H01L31/18 ,  H01L23/544 ,  H01L27/146

CPC classification number: H01L31/1876 ,  H01L23/544 ,  H01L27/14621 ,  H01L27/14627 ,  H01L27/14636 ,  H01L27/1464 ,  H01L27/14683 ,  H01L27/14687 ,  H01L31/186 ,  H01L31/1888 ,  H01L2223/54426

Abstract: A method includes forming image sensors in a semiconductor substrate. A first alignment mark is formed close to a front side of the semiconductor substrate. The method further includes performing a backside polishing process to thin the semiconductor substrate, forming a second alignment mark on the backside of the semiconductor substrate, and forming a feature on the backside of the semiconductor substrate. The feature is formed using the second alignment mark for alignment.

公开(公告)号：US12041771B2

公开(公告)日：2024-07-16

申请号：US17815043

申请日：2022-07-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yen-Jou Wu ,  Chih-Ming Lee ,  Keng-Ying Liao ,  Ping-Pang Hsieh ,  Su-Yu Yeh ,  Hsin-Hui Lin ,  Yu-Liang Wang

IPC: H01L29/788 ,  G11C8/14 ,  H01L29/423 ,  H01L29/66 ,  H10B41/10 ,  H10B41/35

CPC classification number: H10B41/35 ,  G11C8/14 ,  H01L29/42324 ,  H01L29/66825 ,  H01L29/788 ,  H10B41/10

Abstract: The present disclosure describes a patterning process for a strap region in a memory cell for the removal of material between polysilicon lines. The patterning process includes depositing a first hard mask layer in a divot formed on a top portion of a polysilicon layer interposed between a first polysilicon gate structure and a second polysilicon gate; depositing a second hard mask layer on the first hard mask layer. The patterning process also includes performing a first etch to remove the second hard mask layer and a portion of the second hard mask layer from the divot; performing a second etch to remove the second hard mask layer from the divot; and performing a third etch to remove the polysilicon layer not covered by the first and second hard mask layers to form a separation between the first polysilicon gate structure and the second polysilicon structure.