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    Memory Array Word Line Routing
    2.
    发明申请
    Memory Array Word Line Routing 有权

    公开(公告)号：US20210398568A1

    公开(公告)日：2021-12-23

    申请号：US17015679

    申请日：2020-09-09

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Meng-Han Lin ,  Chenchen Jacob Wang ,  Yi-Ching Liu ,  Han-Jong Chia ,  Sai-Hooi Yeong ,  Yu-Ming Lin ,  Yih Wang

    IPC: G11C5/06 ,  H01L27/11587 ,  H01L29/24 ,  H01L27/11597 ,  H01L29/78

    Abstract: Routing arrangements for 3D memory arrays and methods of forming the same are disclosed. In an embodiment, a memory array includes a ferroelectric (FE) material contacting a first word line; an oxide semiconductor (OS) layer contacting a source line and a bit line, the FE material being disposed between the OS layer and the first word line; a dielectric material contacting the FE material, the FE material being between the dielectric material and the first word line; an inter-metal dielectric (IMD) over the first word line; a first contact extending through the IMD to the first word line, the first contact being electrically coupled to the first word line; a second contact extending through the dielectric material and the FE material; and a first conductive line electrically coupling the first contact to the second contact.

    System and method for scheduling semiconductor lot to fabrication tool
    3.
    发明授权
    System and method for scheduling semiconductor lot to fabrication tool 有权

    公开(公告)号：US11042148B2

    公开(公告)日：2021-06-22

    申请号：US15992207

    申请日：2018-05-30

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Lin-Kai Huang ,  Wei-Chi Su ,  Yi-Ching Liu ,  Cheng-Hsuan Liu

    IPC: G05B19/418 ,  H01L21/67 ,  H01L21/66

    Abstract: In the disclosure, a scheduled route of a lot may be rescheduled to another fabrication tool performing the same fabrication processes as to expand the production line and throughput. The controlling method includes at least the following steps. The lot is scheduled with a predetermined route having a plurality of fabrication tools configured to process the lot with a plurality of fabrication processes in a sequence. The lot is monitored as the lot is being processed by the fabrication tools in each of the fabrication processes, and inspection data is generated for each fabrication process. The lot is rescheduled to another fabrication tool outside of the predetermined route for one of the fabrication processes according to a release rule and the inspection data.

    SYSTEM AND METHOD FOR SCHEDULING SEMICONDUCTOR LOT TO FABRICATION TOOL
    4.
    发明申请
    SYSTEM AND METHOD FOR SCHEDULING SEMICONDUCTOR LOT TO FABRICATION TOOL 审中-公开

    公开(公告)号：US20190155260A1

    公开(公告)日：2019-05-23

    申请号：US15992207

    申请日：2018-05-30

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Lin-Kai Huang ,  Wei-Chi Su ,  Yi-Ching Liu ,  Cheng-Hsuan Liu

    IPC: G05B19/418 ,  H01L21/66 ,  H01L21/67

    Abstract: In the disclosure, a scheduled route of a lot may be rescheduled to another fabrication tool performing the same fabrication processes as to expand the production line and throughput. The controlling method includes at least the following steps. The lot is scheduled with a predetermined route having a plurality of fabrication tools configured to process the lot with a plurality of fabrication processes in a sequence. The lot is monitored as the lot is being processed by the fabrication tools in each of the fabrication processes, and inspection data is generated for each fabrication process. The lot is rescheduled to another fabrication tool outside of the predetermined route for one of the fabrication processes according to a release rule and the inspection data.

    Memory device
    8.
    发明授权
    Memory device 有权

    公开(公告)号：US11423960B2

    公开(公告)日：2022-08-23

    申请号：US17085398

    申请日：2020-10-30

    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

    Inventor： Meng-Sheng Chang ,  Chia-En Huang ,  Yi-Ching Liu ,  Yih Wang

    IPC: G11C7/10 ,  G11C8/14 ,  G11C7/18 ,  G11C8/08 ,  G11C7/12

    Abstract: A memory device is disclosed, including a first switch and multiple first memory cells that are arranged in a first column, a second switch and multiple second memory cells that are arranged in a second column, a first data line and a second data line. The first data line is coupled to the first memory cells and the second memory cells. The second data line is coupled connected to the first memory cells and the second memory cells. The first switch transmits a data signal in the first data line in response to a control signal. The second switch outputs the data signal received from the second data line in response to the control signal.

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