公开(公告)号：US11631652B2

公开(公告)日：2023-04-18

申请号：US16663362

申请日：2019-10-25

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ying-Jui Huang ,  Ching-Hua Hsieh ,  Chien-Ling Hwang ,  Chia-Sheng Huang

IPC: H01L23/00 ,  H01L21/67 ,  H01L21/68 ,  H01L21/82

Abstract: A method and an apparatus for bonding semiconductor substrates are provided. The method includes at least the following steps. A first position of a first semiconductor substrate on a first support is gauged by a gauging component embedded in the first support and a first sensor facing towards the gauging component. A second semiconductor substrate is transferred to a position above the first semiconductor substrate by a second support. A second position of the second semiconductor substrate is gauged by a second sensor mounted on the second support and located above the first support. The first semiconductor substrate is positioned based on the second position of the second semiconductor substrate. The second semiconductor substrate is bonded to the first semiconductor substrate.

公开(公告)号：US20220130794A1

公开(公告)日：2022-04-28

申请号：US17646816

申请日：2022-01-03

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ying-Jui Huang ,  Chien Ling Hwang ,  Chih-Wei Lin ,  Ching-Hua Hsieh ,  Chung-Shi Liu ,  Chen-Hua Yu

IPC: H01L23/00 ,  H01L21/48 ,  H01L21/56 ,  H01L21/683 ,  H01L23/31 ,  H01L23/538

Abstract: A method includes placing a first package component and a second package component over a carrier. The first conductive pillars of the first package component and second conductive pillars of the second package component face the carrier. The method further includes encapsulating the first package component and the second package component in an encapsulating material, de-bonding the first package component and the second package component from the carrier, planarizing the first conductive pillars, the second conductive pillars, and the encapsulating material, and forming redistribution lines to electrically couple to the first conductive pillars and the second conductive pillars.

公开(公告)号：US09984960B2

公开(公告)日：2018-05-29

申请号：US15215598

申请日：2016-07-21

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chien-Ling Hwang ,  Ching-Hua Hsieh ,  Hsin-Hung Liao ,  Ying-Jui Huang

IPC: H01L23/52 ,  H01L23/498 ,  H01L21/683 ,  H01L21/48 ,  H01L23/00 ,  H01L21/60

CPC classification number: H01L23/49805 ,  H01L21/4846 ,  H01L21/486 ,  H01L21/6835 ,  H01L23/49827 ,  H01L24/02 ,  H01L24/13 ,  H01L24/16 ,  H01L24/73 ,  H01L2021/60022 ,  H01L2221/68359 ,  H01L2224/02379 ,  H01L2224/024 ,  H01L2224/1301 ,  H01L2224/16235 ,  H01L2224/73253

Abstract: Provided is an integrated fan-out package including a die, a first redistribution circuit structure, a second redistribution circuit structure, a plurality of solder joints, a plurality of conductive posts, and an insulating encapsulation. The first redistribution circuit structure and the second redistribution circuit structure are formed respectively over a back surface and an active surface of the die to sandwich the die. The solder joints are formed aside the die and connected to the first redistribution circuit structure. The conductive posts are formed on the solder joints and connected to the second redistribution circuit structure, and connected to the first redistribution circuit structure through the solder joints. A plurality of sidewalls of the die, a plurality of sidewalls of the conductive posts, and a plurality of sidewalls of the solder joints are encapsulated by the insulating encapsulation. A fabricating process of the integrated fan-out package is also provided.

公开(公告)号：US11094561B2

公开(公告)日：2021-08-17

申请号：US16896039

申请日：2020-06-08

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chien-Ling Hwang ,  Bor-Ping Jang ,  Chung-Shi Liu ,  Hsin-Hung Liao ,  Ying-Jui Huang

IPC: H01L21/56 ,  H01L23/482 ,  H01L23/31 ,  H01L21/48 ,  H01L23/498 ,  H01L21/60 ,  H01L21/603 ,  H01L23/538

Abstract: A semiconductor package structure includes a molding compound, a micro pin extending through the molding compound, and a die surrounded by the molding compound. The micro pin has a top surface, a bottom surface, and a sidewall extending from the bottom surface to the top surface of the micro pin. The sidewall of the micro pin has a first portion and a second portion. The first portion of the sidewall is adjacent to the bottom surface of the micro pin and free of the molding compound. The second portion of the sidewall is adjacent to the top surface of the micro pin and in contact with the molding compound.

公开(公告)号：US10679866B2

公开(公告)日：2020-06-09

申请号：US14622484

申请日：2015-02-13

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chien-Ling Hwang ,  Bor-Ping Jang ,  Chung-Shi Liu ,  Hsin-Hung Liao ,  Ying-Jui Huang

IPC: H01L21/56 ,  H01L23/482 ,  H01L23/31 ,  H01L23/498 ,  H01L21/48 ,  H01L21/60 ,  H01L21/603 ,  H01L23/538

Abstract: A semiconductor package includes a carrier, at least and adhesive portion, a plurality of micro pins and a die. The carrier has a first surface and second surface opposite to the first surface. The adhesive portion is disposed on the first surface, and the plurality of the micro pins is disposed in the adhesive portions. The die is disposed on the remaining adhesive portion free of the micro pins.

公开(公告)号：US12300659B2

公开(公告)日：2025-05-13

申请号：US17646816

申请日：2022-01-03

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ying-Jui Huang ,  Chien Ling Hwang ,  Chih-Wei Lin ,  Ching-Hua Hsieh ,  Chung-Shi Liu ,  Chen-Hua Yu

IPC: H01L23/31 ,  H01L21/48 ,  H01L21/56 ,  H01L21/683 ,  H01L23/00 ,  H01L23/538

Abstract: A method includes placing a first package component and a second package component over a carrier. The first conductive pillars of the first package component and second conductive pillars of the second package component face the carrier. The method further includes encapsulating the first package component and the second package component in an encapsulating material, de-bonding the first package component and the second package component from the carrier, planarizing the first conductive pillars, the second conductive pillars, and the encapsulating material, and forming redistribution lines to electrically couple to the first conductive pillars and the second conductive pillars.

公开(公告)号：US20220285310A1

公开(公告)日：2022-09-08

申请号：US17664484

申请日：2022-05-23

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chen-Hua Yu ,  Ying-Jui Huang ,  Chih-Hang Tung ,  Tung-Liang Shao ,  Ching-Hua Hsieh ,  Chien Ling Hwang ,  Yi-Li Hsiao ,  Su-Chun Yang

IPC: H01L23/00 ,  H01L21/48 ,  H01L25/00

Abstract: A method includes picking up a first package component, removing an oxide layer on an electrical connector of the first package component, placing the first package component on a second package component after the oxide layer is removed, and bonding the first package component to the second package component.

公开(公告)号：US11139177B2

公开(公告)日：2021-10-05

申请号：US16896038

申请日：2020-06-08

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chien-Ling Hwang ,  Bor-Ping Jang ,  Chung-Shi Liu ,  Hsin-Hung Liao ,  Ying-Jui Huang

IPC: H01L21/56 ,  H01L23/482 ,  H01L23/31 ,  H01L21/48 ,  H01L23/498 ,  H01L21/60 ,  H01L21/603 ,  H01L23/538

Abstract: A method of fabricating a semiconductor package structure is provided. The method includes applying a plurality of first adhesive portions onto a carrier; applying a second adhesive portion onto the carrier; disposing a plurality of micro pins respectively in the first adhesive portions, such that each of the micro pins has a first portion embedded in a corresponding one of the first adhesive portions and a second portion protruding from said corresponding one of the first adhesive portions; bonding a die to the second adhesive portion; forming a molding compound surrounding the micro pins and the die; and removing the carrier from the molding compound after forming the molding compound.

公开(公告)号：US11101232B2

公开(公告)日：2021-08-24

申请号：US16173992

申请日：2018-10-29

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Ying-Jui Huang ,  Chung-Shi Liu ,  Hsin-Hung Liao ,  Chien-Ling Hwang

IPC: H01L23/00 ,  C25D1/00 ,  C25D1/22

Abstract: A conductive micro pin includes a body having a first end surface, a second end surface, a first side surface connecting the first end surface and the second end surface, and a first corner between the first end surface and the first side surface, in which the first side surface is substantially flat, and the first corner is substantially rounded.

公开(公告)号：US20200227379A1

公开(公告)日：2020-07-16

申请号：US16663362

申请日：2019-10-25

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ying-Jui Huang ,  Ching-Hua Hsieh ,  Chien-Ling Hwang ,  Chia-Sheng Huang

IPC: H01L23/00 ,  H01L21/82 ,  H01L21/68 ,  H01L21/67

Abstract: A method and an apparatus for bonding semiconductor substrates are provided. The method includes at least the following steps. A first position of a first semiconductor substrate on a first support is gauged by a gauging component embedded in the first support and a first sensor facing towards the gauging component. A second semiconductor substrate is transferred to a position above the first semiconductor substrate by a second support. A second position of the second semiconductor substrate is gauged by a second sensor mounted on the second support and located above the first support. The first semiconductor substrate is positioned based on the second position of the second semiconductor substrate. The second semiconductor substrate is bonded to the first semiconductor substrate.