公开(公告)号：US20220285310A1

公开(公告)日：2022-09-08

申请号：US17664484

申请日：2022-05-23

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chen-Hua Yu ,  Ying-Jui Huang ,  Chih-Hang Tung ,  Tung-Liang Shao ,  Ching-Hua Hsieh ,  Chien Ling Hwang ,  Yi-Li Hsiao ,  Su-Chun Yang

IPC: H01L23/00 ,  H01L21/48 ,  H01L25/00

Abstract: A method includes picking up a first package component, removing an oxide layer on an electrical connector of the first package component, placing the first package component on a second package component after the oxide layer is removed, and bonding the first package component to the second package component.

公开(公告)号：US20210050229A1

公开(公告)日：2021-02-18

申请号：US16732501

申请日：2020-01-02

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chen-Hua Yu ,  Chien Ling Hwang

IPC: H01L21/56 ,  H01L21/683 ,  H01L23/00

Abstract: A method includes coating a release film over a carrier. The carrier includes a first material having a first Coefficient of Thermal Expansion (CTE), and a second material having a second CTE different from the first CTE. The method further includes placing a device die over the release film, encapsulating the device die in an encapsulant, and planarizing the encapsulant until the device die is revealed.

公开(公告)号：US10804234B2

公开(公告)日：2020-10-13

申请号：US16382503

申请日：2019-04-12

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chien Ling Hwang ,  Yeong-Jyh Lin ,  Bor-Ping Jang ,  Hsiao-Chung Liang

IPC: H01L25/10 ,  H01L23/14 ,  H01L23/00 ,  H01L23/498 ,  H01L21/48

Abstract: The present disclosure, in some embodiments, relates to a semiconductor structure. The semiconductor structure includes a substrate and a first conductive pad arranged over the substrate. A boundary structure is on an upper surface of the substrate around the first conductive pad. The boundary structure has one or more sidewalls defining an opening with a round shape over the first conductive pad.

公开(公告)号：US20240371726A1

公开(公告)日：2024-11-07

申请号：US18778763

申请日：2024-07-19

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shu-Rong Chun ,  Kuo-Lung Pan ,  Pei-Hsuan Lee ,  Chien Ling Hwang ,  Yu-Chia Lai ,  Tin-Hao Kuo ,  Hao-Yi Tsai ,  Chen-Hua Yu

IPC: H01L23/40 ,  H01L23/00

Abstract: In an embodiment, a device includes: a package component including integrated circuit dies, an encapsulant around the integrated circuit dies, a redistribution structure over the encapsulant and the integrated circuit dies, and sockets over the redistribution structure; a mechanical brace physically coupled to the sockets, the mechanical brace having openings, each one of the openings exposing a respective one of the sockets; a thermal module physically and thermally coupled to the encapsulant and the integrated circuit dies; and bolts extending through the thermal module, the mechanical brace, and the package component.

公开(公告)号：US11410953B2

公开(公告)日：2022-08-09

申请号：US16983282

申请日：2020-08-03

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ming-Che Ho ,  Yi-Wen Wu ,  Chien Ling Hwang ,  Hung-Jui Kuo ,  Chung-Shi Liu

IPC: H01L21/56 ,  H01L27/112 ,  H01L23/31 ,  H01L21/48 ,  H01L21/3105 ,  H01L25/065 ,  H01L27/02 ,  H01L23/00

Abstract: A via or pillar structure, and a method of forming, is provided. In an embodiment, a polymer layer is formed having openings exposing portions of an underlying conductive pad. A conductive layer is formed over the polymer layer, filling the openings. The dies are covered with a molding material and a planarization process is performed to form pillars in the openings. In another embodiment, pillars are formed and then a polymer layer is formed over the pillars. The dies are covered with a molding material and a planarization process is performed to expose the pillars. In yet another embodiment, pillars are formed and a molding material is formed directly over the pillars. A planarization process is performed to expose the pillars. In still yet another embodiment, bumps are formed and a molding material is formed directly over the bumps. A planarization process is performed to expose the bumps.

公开(公告)号：US20190237422A1

公开(公告)日：2019-08-01

申请号：US16382503

申请日：2019-04-12

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chien Ling Hwang ,  Yeong-Jyh Lin ,  Bor-Ping Jang ,  Hsiao-Chung Liang

IPC: H01L23/00 ,  H01L23/498 ,  H01L25/10 ,  H01L21/48 ,  H01L23/14

Abstract: The present disclosure, in some embodiments, relates to a semiconductor structure. The semiconductor structure includes a substrate and a first conductive pad arranged over the substrate. A boundary structure is on an upper surface of the substrate around the first conductive pad. The boundary structure has one or more sidewalls defining an opening with a round shape over the first conductive pad.

公开(公告)号：US20230387039A1

公开(公告)日：2023-11-30

申请号：US17881128

申请日：2022-08-04

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Sung-Yueh Wu ,  Jen-Chun Liao ,  Mao-Yen Chang ,  Yu-Chia Lai ,  Chien Ling Hwang ,  Ching-Hua Hsieh

IPC: H01L23/00 ,  H01L23/31 ,  H01L23/498 ,  H01L23/367 ,  H01L23/552 ,  H01L21/56 ,  H01L21/48

CPC classification number: H01L23/562 ,  H01L23/3107 ,  H01L23/49822 ,  H01L23/49838 ,  H01L23/367 ,  H01L23/552 ,  H01L21/56 ,  H01L21/4857

Abstract: A semiconductor package includes a first package component comprising: an integrated circuit die; an encapsulant surrounding the integrated circuit die; and a fan-out structure electrically connected to the integrated circuit die, wherein a first opening extends completely through the fan-out structure and at least partially through the encapsulant in a cross-sectional view, and wherein the encapsulant at least completely surrounds the first opening in a top-down view. The semiconductor package further includes a package substrate bonded to the first package component.

公开(公告)号：US20210098318A1

公开(公告)日：2021-04-01

申请号：US17121232

申请日：2020-12-14

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Tsung-Ding Wang ,  An-Jhih Su ,  Chien Ling Hwang ,  Jung Wei Cheng ,  Hsin-Yu Pan ,  Chen-Hua Yu

IPC: H01L23/04 ,  H01L23/42 ,  H01L23/367 ,  H01L23/00 ,  H01L23/10 ,  H01L21/56 ,  H01L25/065

Abstract: An apparatus comprising a first substrate, a dam structure disposed on a first side of the first substrate, and an integrated circuit (IC) memory chip coupled to the first side of the first substrate by a plurality of first conductive members. A second substrate is coupled to a second side of the first substrate by a plurality of second conductive members. A lid coupled to the second substrate encloses the IC memory chip and the first substrate. A thermal interface material (TIM) is coupled between the lid and the dam structure.

公开(公告)号：US20200328169A1

公开(公告)日：2020-10-15

申请号：US16915780

申请日：2020-06-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chen-Hua Yu ,  Yen-Chang Hu ,  Ching-Wen Hsiao ,  Mirng-Ji Lii ,  Chung-Shi Liu ,  Chien Ling Hwang ,  Chih-Wei Lin ,  Chen-Shien Chen

IPC: H01L23/00 ,  H01L23/29 ,  H01L23/31 ,  H01L21/56 ,  H01L23/538

Abstract: A method embodiment includes forming a sacrificial film layer over a top surface of a die, the die having a contact pad at the top surface. The die is attached to a carrier, and a molding compound is formed over the die and the sacrificial film layer. The molding compound extends along sidewalls of the die. The sacrificial film layer is exposed. The contact pad is exposed by removing at least a portion of the sacrificial film layer. A first polymer layer is formed over the die, and a redistribution layer (RDL) is formed over the die and electrically connects to the contact pad.

公开(公告)号：US09768142B2

公开(公告)日：2017-09-19

申请号：US13944334

申请日：2013-07-17

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Yeong-Jyh Lin ,  Hsin-Hung Liao ,  Chien Ling Hwang ,  Bor-Ping Jang ,  Hsiao-Chung Liang ,  Chung-Shi Liu

IPC: H01L23/00 ,  H01L21/48 ,  H01L25/03 ,  H01L25/10 ,  H01L25/00 ,  H01L23/498 ,  H01L25/065

CPC classification number: H01L24/81 ,  H01L21/4853 ,  H01L23/49811 ,  H01L24/16 ,  H01L24/29 ,  H01L24/32 ,  H01L24/45 ,  H01L24/48 ,  H01L25/03 ,  H01L25/0657 ,  H01L25/105 ,  H01L25/50 ,  H01L2224/16225 ,  H01L2224/2919 ,  H01L2224/32145 ,  H01L2224/45147 ,  H01L2224/48225 ,  H01L2224/73265 ,  H01L2225/0651 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/12042 ,  H01L2924/1305 ,  H01L2924/13091 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45015 ,  H01L2924/207

Abstract: Embodiments of mechanisms for forming a package are provided. The package includes a substrate and a contact pad formed on the substrate. The package also includes a conductive pillar bonded to the contact pad through solder formed between the conductive pillar and the contact pad. The solder is in direct contact with the conductive pillar.