公开(公告)号：US11545584B2

公开(公告)日：2023-01-03

申请号：US17230906

申请日：2021-04-14

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Yong-Sheng Huang ,  Ming-Chyi Liu

IPC: H01L29/792 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L21/28 ,  H01L21/762

Abstract: A memory device includes an active region, a select gate, a control gate, and a blocking layer. The active region includes a bottom portion and a protruding portion protruding from the bottom portion. A source is in the bottom portion and a drain is in the protruding portion. The select gate is above the bottom portion. A top surface of the select gate is lower than a top surface of the protruding portion. The control gate is above the bottom portion. The blocking layer is between the select gate and the control gate.

公开(公告)号：US20210066323A1

公开(公告)日：2021-03-04

申请号：US16800167

申请日：2020-02-25

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yong-Sheng Huang ,  Ming Chyi Liu ,  Chih-Pin Huang

IPC: H01L27/11521 ,  H01L23/528 ,  H01L23/522 ,  H01L29/788 ,  H01L21/768 ,  H01L21/311 ,  H01L21/762 ,  H01L21/3213 ,  H01L21/28 ,  H01L29/423 ,  H01L29/66

Abstract: Various embodiments of the present disclosure are directed towards a method for opening a source line in a memory device. An erase gate line (EGL) and the source line are formed elongated in parallel. The source line underlies the EGL and is separated from the EGL by a dielectric layer. A first etch is performed to form a first opening through the EGL and stops on the dielectric layer. A second etch is performed to thin the dielectric layer at the first opening, wherein the first and second etches are performed with a common mask in place. A silicide process is performed to form a silicide layer on the source line at the first opening, wherein the silicide process comprises a third etch with a second mask in place and extends the first opening through the dielectric layer. A via is formed extending through the EGL to the silicide layer.

公开(公告)号：US11183571B2

公开(公告)日：2021-11-23

申请号：US16745219

申请日：2020-01-16

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Yong-Sheng Huang ,  Ming-Chyi Liu ,  Chih-Ren Hsieh

IPC: H01L29/423 ,  H01L27/11524 ,  H01L27/11519 ,  H01L21/28

Abstract: A semiconductor device includes an erase gate electrode, an erase gate dielectric, first and second floating gate electrodes, first and second control gate electrodes, a first select gate electrode, a second select gate electrode, a common source strap, and a silicide pad. The erase gate electrode is over a first portion of a substrate. The common source strap is over a second portion of the substrate, in which the common source strap and the erase gate electrode are arranged along a second direction perpendicular to the first direction. The silicide pad is under the common source strap and in the second portion of the substrate, wherein a top surface of the silicide pad is flatter than a bottom surface of the erase gate dielectric.

公开(公告)号：US11239245B2

公开(公告)日：2022-02-01

申请号：US16800167

申请日：2020-02-25

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yong-Sheng Huang ,  Ming Chyi Liu ,  Chih-Pin Huang

IPC: H01L27/11521 ,  H01L23/528 ,  H01L23/522 ,  H01L29/788 ,  H01L21/768 ,  H01L29/66 ,  H01L21/311 ,  H01L21/762 ,  H01L21/3213 ,  H01L21/28 ,  H01L29/423

Abstract: Various embodiments of the present disclosure are directed towards a method for opening a source line in a memory device. An erase gate line (EGL) and the source line are formed elongated in parallel. The source line underlies the EGL and is separated from the EGL by a dielectric layer. A first etch is performed to form a first opening through the EGL and stops on the dielectric layer. A second etch is performed to thin the dielectric layer at the first opening, wherein the first and second etches are performed with a common mask in place. A silicide process is performed to form a silicide layer on the source line at the first opening, wherein the silicide process comprises a third etch with a second mask in place and extends the first opening through the dielectric layer. A via is formed extending through the EGL to the silicide layer.

公开(公告)号：US11417741B2

公开(公告)日：2022-08-16

申请号：US16953921

申请日：2020-11-20

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yong-Sheng Huang ,  Ming Chyi Liu

IPC: H01L29/792 ,  H01L29/423 ,  H01L21/28 ,  H01L27/1157 ,  H01L29/66

Abstract: The present disclosure relates to an integrated chip comprising a substrate having a first top surface disposed at a first height, a second top surface disposed at a second height that is less than the first height, and a connecting surface extending from the first top surface to the second top surface. A first source/drain region is disposed along the first top surface of the substrate. A second source/drain region is disposed along the second top surface of the substrate and is laterally separated from the first source/drain region by a channel region of the substrate. A gate structure is arranged between the first source/drain region and the second source/drain region. The gate structure extends from over the first top surface of the substrate to over the connecting surface of the substrate. The gate structure also extends below the first top surface of the substrate.

公开(公告)号：US20220165859A1

公开(公告)日：2022-05-26

申请号：US16953921

申请日：2020-11-20

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yong-Sheng Huang ,  Ming Chyi Liu

IPC: H01L29/423 ,  H01L21/28 ,  H01L29/66 ,  H01L29/792 ,  H01L27/1157

Abstract: The present disclosure relates to an integrated chip comprising a substrate having a first top surface disposed at a first height, a second top surface disposed at a second height that is less than the first height, and a connecting surface extending from the first top surface to the second top surface. A first source/drain region is disposed along the first top surface of the substrate. A second source/drain region is disposed along the second top surface of the substrate and is laterally separated from the first source/drain region by a channel region of the substrate. A gate structure is arranged between the first source/drain region and the second source/drain region. The gate structure extends from over the first top surface of the substrate to over the connecting surface of the substrate. The gate structure also extends below the first top surface of the substrate.

公开(公告)号：US10998450B1

公开(公告)日：2021-05-04

申请号：US16734095

申请日：2020-01-03

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Yong-Sheng Huang ,  Ming-Chyi Liu

IPC: H01L29/792 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L21/28 ,  H01L21/762

Abstract: A memory device includes an active region, a select gate, a control gate, and a blocking layer. The active region includes a bottom portion and a protruding portion protruding from the bottom portion. A source is in the bottom portion and a drain is in the protruding portion. The select gate is above the bottom portion. A top surface of the select gate is lower than a top surface of the protruding portion. The control gate is above the bottom portion. The blocking layer is between the select gate and the control gate.

公开(公告)号：US11742434B2

公开(公告)日：2023-08-29

申请号：US18092423

申请日：2023-01-02

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Yong-Sheng Huang ,  Ming-Chyi Liu

IPC: H01L29/792 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L21/28 ,  H01L21/762

CPC classification number: H01L29/7926 ,  H01L21/76224 ,  H01L29/0653 ,  H01L29/40114 ,  H01L29/42344 ,  H01L29/66666 ,  H01L29/66833

Abstract: A device includes an active region, a select gate, a control gate, a first metal alloy layer, and a second metal alloy layer. The active region has a source region and a drain region. The select gate is over the active region and between the source region and the drain region. The control gate is over the active region and between the source region and the select gate. The first metal alloy layer is in contact with the source region. The second metal alloy layer is in contact with the drain region and higher than a top surface of the control gate.

公开(公告)号：US10784278B2

公开(公告)日：2020-09-22

申请号：US16171353

申请日：2018-10-25

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yong-Sheng Huang ,  Ming-Chyi Liu

IPC: H01L27/11582 ,  H01L27/11568 ,  H01L21/28 ,  H01L23/528

Abstract: A memory device and a manufacturing method are provided. The memory device includes a plurality of memory cells stacked on a substrate. The memory cell includes two conductive patterns, a channel pillar, a gate pattern and a charge storage layer. The two conductive patterns are stacked on the substrate. The channel pillar extends between the two conductive patterns along a stacking direction of the two conductive patterns, and is electrically connected with the two conductive patterns. The gate pattern is disposed between the two conductive patterns and located at a sidewall of the channel pillar. The charge storage layer is disposed between the gate pattern and the channel pillar.

公开(公告)号：US20200035701A1

公开(公告)日：2020-01-30

申请号：US16171353

申请日：2018-10-25

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yong-Sheng Huang ,  Ming-Chyi Liu

IPC: H01L27/11582 ,  H01L27/11568 ,  H01L21/28 ,  H01L23/528

Abstract: A memory device and a manufacturing method are provided. The memory device includes a plurality of memory cells stacked on a substrate. The memory cell includes two conductive patterns, a channel pillar, a gate pattern and a charge storage layer. The two conductive patterns are stacked on the substrate. The channel pillar extends between the two conductive patterns along a stacking direction of the two conductive patterns, and is electrically connected with the two conductive patterns. The gate pattern is disposed between the two conductive patterns and located at a sidewall of the channel pillar. The charge storage layer is disposed between the gate pattern and the channel pillar.