公开(公告)号：US20220013482A1

公开(公告)日：2022-01-13

申请号：US17100010

申请日：2020-11-20

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hung-Shu Huang ,  Ming-Chyi Liu

IPC: H01L23/00

Abstract: A method includes depositing a first dielectric layer covering an electrical connector, depositing a second dielectric layer over the first dielectric layer, and performing a first etching process to etch-through the second dielectric layer and the first dielectric layer. An opening is formed in the first dielectric layer and the second dielectric layer to reveal the electrical connector. A second etching process is performed to laterally etch the first dielectric layer and the second dielectric layer. An isolation layer is deposited to extend into the opening. The isolation layer has a vertical portion and a first horizontal portion in the opening, and a second horizontal portion overlapping the second dielectric layer. An anisotropic etching process is performed on the isolation layer, with the vertical portion of the isolation layer being left in the opening.

公开(公告)号：US11183571B2

公开(公告)日：2021-11-23

申请号：US16745219

申请日：2020-01-16

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Yong-Sheng Huang ,  Ming-Chyi Liu ,  Chih-Ren Hsieh

IPC: H01L29/423 ,  H01L27/11524 ,  H01L27/11519 ,  H01L21/28

Abstract: A semiconductor device includes an erase gate electrode, an erase gate dielectric, first and second floating gate electrodes, first and second control gate electrodes, a first select gate electrode, a second select gate electrode, a common source strap, and a silicide pad. The erase gate electrode is over a first portion of a substrate. The common source strap is over a second portion of the substrate, in which the common source strap and the erase gate electrode are arranged along a second direction perpendicular to the first direction. The silicide pad is under the common source strap and in the second portion of the substrate, wherein a top surface of the silicide pad is flatter than a bottom surface of the erase gate dielectric.

公开(公告)号：US10276613B2

公开(公告)日：2019-04-30

申请号：US15942512

申请日：2018-03-31

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ming-Chyi Liu

IPC: H01L27/146

Abstract: An image sensor and a method for forming an image sensor are provided. The image sensor includes a substrate, and the substrate includes a pixel region, a peripheral region and a boundary region, and the boundary region is formed between the pixel region and the peripheral region. The image sensor also includes a first gate stack structure formed in the pixel region and a second gate stack structure formed in the peripheral region. The second gate stack structure includes a high-k dielectric layer and a first metal layer.

公开(公告)号：US20190122962A1

公开(公告)日：2019-04-25

申请号：US16221767

申请日：2018-12-17

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yuan-Tai Tseng ,  Chia-Shiung Tsai ,  Chung-Yen Chou ,  Ming-Chyi Liu

IPC: H01L23/485 ,  H01C17/075 ,  H01C7/00 ,  H01L21/768 ,  H01L23/522 ,  H01L49/02 ,  H01L21/70

Abstract: A novel integrated circuit and method thereof are provided. The integrated circuit includes a plurality of first interconnect pads, a plurality of second interconnect pads, a first inter-level dielectric layer, a thin film resistor, and at least two end-caps. The end-caps, which are connectors for the thin film resistor, are positioned at the same level with the plurality of second interconnect pads. Therefore, an electrical connection between the end-caps and the plurality of second interconnect pads can be formed by directly connection of them. An integrated circuit with a thin film resistor can be made in a cost benefit way accordingly, so as to overcome disadvantages mentioned above.

公开(公告)号：US10998450B1

公开(公告)日：2021-05-04

申请号：US16734095

申请日：2020-01-03

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Yong-Sheng Huang ,  Ming-Chyi Liu

IPC: H01L29/792 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L21/28 ,  H01L21/762

Abstract: A memory device includes an active region, a select gate, a control gate, and a blocking layer. The active region includes a bottom portion and a protruding portion protruding from the bottom portion. A source is in the bottom portion and a drain is in the protruding portion. The select gate is above the bottom portion. A top surface of the select gate is lower than a top surface of the protruding portion. The control gate is above the bottom portion. The blocking layer is between the select gate and the control gate.

公开(公告)号：US10903366B1

公开(公告)日：2021-01-26

申请号：US16573888

申请日：2019-09-17

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Sheng-Chieh Chen ,  Ming-Chyi Liu

IPC: H01L29/78 ,  H01L27/1157 ,  H01L29/66 ,  H01L29/792 ,  H01L29/423 ,  H01L21/28

Abstract: A process is provided to fabricate a finFET device. A gate electrode layer is positioned over a dielectric layer. The gate electrode layer and the dielectric layer are both positioned over and surrounding a fin-shaped semiconductor structure. A gate electrode is formed from the gate electrode layer through a two-step patterning process. At a first patterning step, an upper portion of the gate electrode layer is patterned. Then a dielectric film is formed covering the patterned upper portion of the gate electrode layer. After the dielectric film is formed, a second patterning process is performed to pattern a lower portion of gate electrode layer.

公开(公告)号：US09978761B2

公开(公告)日：2018-05-22

申请号：US15216872

申请日：2016-07-22

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ming-Chyi Liu ,  Shih-Chang Liu ,  Sheng-Chieh Chen

IPC: H01L27/105 ,  H01L27/11526 ,  H01L27/11519 ,  H01L27/11521 ,  H01L27/11556

CPC classification number: H01L27/11526 ,  H01L27/1052 ,  H01L27/11519 ,  H01L27/11521 ,  H01L27/11556 ,  H01L29/42328

Abstract: The present disclosure relates to an improved integrated circuit having an embedded flash memory device with a word line having its height reduced, and associated processing methods. In some embodiments, the flash memory device includes a gate stack separated from a substrate by a gate dielectric. The gate stack includes a control gate separated from a floating gate by a control gate dielectric. An erase gate is disposed on a first side of the gate stack and a word line is disposed on a second side of the gate stack that is opposite to the first side. The word line has a height that monotonically increases from an outer side opposite to the gate stack to an inner side closer to the gate stack. A word line height at the outer side is smaller than an erase gate height.

公开(公告)号：US20240363563A1

公开(公告)日：2024-10-31

申请号：US18766279

申请日：2024-07-08

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hung-Shu Huang ,  Ming-Chyi Liu

IPC: H01L23/00 ,  H01L23/31 ,  H01L23/495 ,  H01L23/498 ,  H01L23/532

CPC classification number: H01L24/05 ,  H01L23/3171 ,  H01L23/4952 ,  H01L23/49866 ,  H01L23/53295 ,  H01L24/03 ,  H01L2224/04042 ,  H01L2224/0558 ,  H01L2224/05686

Abstract: A method includes depositing a first dielectric layer covering an electrical connector, depositing a second dielectric layer over the first dielectric layer, and performing a first etching process to etch-through the second dielectric layer and the first dielectric layer. An opening is formed in the first dielectric layer and the second dielectric layer to reveal the electrical connector. A second etching process is performed to laterally etch the first dielectric layer and the second dielectric layer. An isolation layer is deposited to extend into the opening. The isolation layer has a vertical portion and a first horizontal portion in the opening, and a second horizontal portion overlapping the second dielectric layer. An anisotropic etching process is performed on the isolation layer, with the vertical portion of the isolation layer being left in the opening.

公开(公告)号：US11532579B2

公开(公告)日：2022-12-20

申请号：US17100010

申请日：2020-11-20

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hung-Shu Huang ,  Ming-Chyi Liu

IPC: H01L23/00

Abstract: A method includes depositing a first dielectric layer covering an electrical connector, depositing a second dielectric layer over the first dielectric layer, and performing a first etching process to etch-through the second dielectric layer and the first dielectric layer. An opening is formed in the first dielectric layer and the second dielectric layer to reveal the electrical connector. A second etching process is performed to laterally etch the first dielectric layer and the second dielectric layer. An isolation layer is deposited to extend into the opening. The isolation layer has a vertical portion and a first horizontal portion in the opening, and a second horizontal portion overlapping the second dielectric layer. An anisotropic etching process is performed on the isolation layer, with the vertical portion of the isolation layer being left in the opening.

公开(公告)号：US11424255B2

公开(公告)日：2022-08-23

申请号：US16787952

申请日：2020-02-11

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Ming-Chyi Liu ,  Chih-Ren Hsieh ,  Sheng-Chieh Chen

IPC: H01L29/66 ,  H01L27/11521 ,  H01L21/28 ,  H01L21/762 ,  H01L21/311 ,  H01L29/423 ,  H01L21/3213 ,  H01L21/3105 ,  H01L29/788

Abstract: A semiconductor device includes a substrate, an isolation feature, a floating gate, and a control gate. The substrate has a protruding portion. The isolation feature surrounds the protruding portion of the substrate. The floating gate is over the protruding portion of the substrate, in which a sidewall of the floating gate is aligned with a sidewall of the protruding portion of the substrate. The control gate is over the floating gate.