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    AIR SPACER SURROUNDING CONDUCTIVE FEATURES AND METHOD FORMING SAME
    1.
    发明申请
    AIR SPACER SURROUNDING CONDUCTIVE FEATURES AND METHOD FORMING SAME 有权

    公开(公告)号：US20240379414A1

    公开(公告)日：2024-11-14

    申请号：US18782335

    申请日：2024-07-24

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Yi-Nien Su ,  Yu-Yu Chen ,  Kuan-Wei Huang ,  Li-Min Chen

    IPC: H01L21/768 ,  H01L23/522 ,  H01L23/532

    Abstract: A method includes etching a dielectric layer to form an opening. A first conductive feature underlying the dielectric layer is exposed to the opening. A sacrificial spacer layer is deposited to extend into the opening. The sacrificial spacer layer is patterned. A bottom portion of the sacrificial spacer layer at a bottom of the opening is removed to reveal the first conductive feature, and a vertical portion of the sacrificial spacer layer in the opening and on sidewalls of the dielectric layer is left to form a ring. A second conductive feature is formed in the opening. The second conductive feature is encircled by the ring, and is over and electrically coupled to the first conductive feature. At least a portion of the ring is removed to form an air spacer.

    Lithography method to reduce spacing between interconnect wires in interconnect structure
    3.
    发明授权
    Lithography method to reduce spacing between interconnect wires in interconnect structure 有权

    公开(公告)号：US11728209B2

    公开(公告)日：2023-08-15

    申请号：US17126246

    申请日：2020-12-18

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Yi-Nien Su ,  Yu-Yu Chen

    IPC: H01L21/768 ,  H01L21/033

    CPC classification number: H01L21/76816 ,  H01L21/0335 ,  H01L21/0337 ,  H01L21/0338 ,  H01L21/76877

    Abstract: In some embodiments, the present disclosure relates to a method that includes depositing multiple hard mask layers over an interconnect dielectric layer. A first patterning layer is deposited over the multiple hard mask layers, and a first masking structure is formed over the first masking structure. The first masking structure has openings formed by a first extreme ultraviolet (EUV) lithography process. Portions of the first patterning layer are removed according to the first masking structure. A second masking structure is formed within the patterned first patterning layer. A third masking structure is formed over a topmost one of the hard mask layers and has openings formed by a second EUV lithography process. Removal processes are performed to pattern the multiple hard mask layers to form openings in the interconnect dielectric layer, and interconnect wires having rounded corners are formed within the openings of the interconnect dielectric layer.

    SELF-ALIGNED DOUBLE PATTERNING
    4.
    发明申请
    SELF-ALIGNED DOUBLE PATTERNING 有权

    公开(公告)号：US20210125836A1

    公开(公告)日：2021-04-29

    申请号：US17018705

    申请日：2020-09-11

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Kuan-Wei Huang ,  Yu-Yu Chen ,  Jyu-Horng Shieh

    IPC: H01L21/308 ,  H01L21/768 ,  H01L21/311

    Abstract: A method includes patterning a mandrel layer over a target layer to form first mandrels and second mandrels, the first mandrels having a larger width than the second mandrels. A spacer layer is formed over the first mandrels and the second mandrels, and altered so that a thickness of the spacer layer over the first mandrels is greater than a thickness of the spacer layer over the second mandrels. Spacers are formed from the spacer layer which have a greater width adjacent the first mandrels than the spacers which are adjacent the second mandrels. The spacers are used to etch a target layer.

    SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF
    5.
    发明申请
    SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF 审中-公开

    公开(公告)号：US20190115251A1

    公开(公告)日：2019-04-18

    申请号：US16222628

    申请日：2018-12-17

    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

    Inventor： Yan-Jhi HUANG ,  Yu-Yu Chen

    IPC: H01L21/768 ,  H01L21/033 ,  H01L21/311

    CPC classification number: H01L21/76816 ,  H01L21/0332 ,  H01L21/0335 ,  H01L21/0337 ,  H01L21/0338 ,  H01L21/31144 ,  H01L21/76829 ,  H01L21/76877

    Abstract: A method for manufacturing a semiconductor device includes forming a hard mask layer overlying a device layer of a semiconductor device, a mandrel underlayer over hard mask layer, and a mandrel layer over mandrel underlayer. The mandrel layer has a plurality of mandrel lines extending along a first direction. A plurality of openings are formed in mandrel underlayer extending in a second direction substantially perpendicular to first direction. A spacer layer is formed over mandrel underlayer and layer. Spacer layer fills plurality of openings in underlayer. Portions of spacer layer are removed to expose an upper surface of underlayer and mandrel layer, and mandrel layer is removed. By using remaining portions of spacer layer as a mask, underlayer and hard mask layer are removed, to form a hard mask pattern with first hard mask pattern lines extending along first direction and second hard mask pattern lines extending along second direction.

    Air spacer surrounding conductive features and method forming same
    6.
    发明授权
    Air spacer surrounding conductive features and method forming same 有权

    公开(公告)号：US12165914B2

    公开(公告)日：2024-12-10

    申请号：US17369497

    申请日：2021-07-07

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Yi-Nien Su ,  Yu-Yu Chen ,  Kuan-Wei Huang ,  Li-Min Chen

    IPC: H01L21/768 ,  H01L23/522 ,  H01L23/532

    Abstract: A method includes etching a dielectric layer to form an opening. A first conductive feature underlying the dielectric layer is exposed to the opening. A sacrificial spacer layer is deposited to extend into the opening. The sacrificial spacer layer is patterned. A bottom portion of the sacrificial spacer layer at a bottom of the opening is removed to reveal the first conductive feature, and a vertical portion of the sacrificial spacer layer in the opening and on sidewalls of the dielectric layer is left to form a ring. A second conductive feature is formed in the opening. The second conductive feature is encircled by the ring, and is over and electrically coupled to the first conductive feature. At least a portion of the ring is removed to form an air spacer.

    SEMICONDUCTOR DEVICES AND METHODS OF MANUFACTURE
    7.
    发明申请
    SEMICONDUCTOR DEVICES AND METHODS OF MANUFACTURE 有权

    公开(公告)号：US20240387248A1

    公开(公告)日：2024-11-21

    申请号：US18787890

    申请日：2024-07-29

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Kuan-Wei Huang ,  Yu-Yu Chen

    IPC: H01L21/768 ,  H01L21/027 ,  H01L23/522 ,  H01L23/528 ,  H01L23/532

    Abstract: A patterning process that can be utilized in order to help form conductive lines within a dielectric layer of a metallization layer is provided. In an embodiment a first interfacial layer is patterned a first time, the first interfacial layer being located over a first hard mask layer over a dielectric layer, the patterning the first interfacial layer the first time forming a first opening, which is filled with a first dielectric material. The first interfacial layer is patterned a second time, the patterning the first interfacial layer the second time forming second openings in the first interfacial layer, at least one of the second openings exposing the first dielectric material. The first dielectric material is removed, and the dielectric layer is patterned a second time after the removing the first dielectric material using the first interfacial layer as a mask, the patterning the dielectric layer extending the second openings.

    Semiconductor manufacturing system and particle removal method
    10.
    发明授权
    Semiconductor manufacturing system and particle removal method 有权

    公开(公告)号：US11385555B2

    公开(公告)日：2022-07-12

    申请号：US16867762

    申请日：2020-05-06

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Chih-Yuan Yao ,  Yu-Yu Chen ,  Hsiang-Lung Tsou

    IPC: G03F7/20 ,  B08B5/00 ,  B08B6/00

    Abstract: A particle removal method includes loading a particle attracting member with a coating layer into a processing chamber of a processing apparatus. The method also includes fixing the particle attracting member on a holder in the processing chamber in a cleaning cycle. The method also includes attracting particles in the processing chamber by the coating layer of the particle attracting member due to a potential difference between the particles and the coating layer. The particles are attracted to the surface of the coating layer. The method further includes loading the particle attracting member with the coating layer and the attracted particles out of the processing chamber, after the cleaning cycle. In addition, the method includes loading a semiconductor wafer into the processing chamber, and performing a semiconductor process on the semiconductor wafer in the processing chamber. The semiconductor process is performed after the cleaning cycle.

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