公开(公告)号：US20210398975A1

公开(公告)日：2021-12-23

申请号：US17446900

申请日：2021-09-03

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ming-Chi HUANG ,  Ying-Liang CHUANG ,  Ming-Hsi YEH ,  Kuo-Bin HUANG

IPC: H01L27/088 ,  H01L21/8234 ,  H01L21/3213 ,  H01L29/66 ,  H01L29/49 ,  H01L21/311 ,  H01L29/51 ,  H01L29/06 ,  H01L29/423 ,  H01L21/8238 ,  H01L27/092

Abstract: Provided is a metal gate structure and related methods that include performing a metal gate cut process. The metal gate cut process includes a plurality of etching steps. For example, a first anisotropic dry etch is performed, a second isotropic dry etch is performed, and a third wet etch is performed. In some embodiments, the second isotropic etch removes a residual portion of a metal gate layer including a metal containing layer. In some embodiments, the third etch removes a residual portion of a dielectric layer.

公开(公告)号：US20200279766A1

公开(公告)日：2020-09-03

申请号：US16876287

申请日：2020-05-18

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wang-Hua LIN ,  Chun-Liang TAI ,  Chun-Hsiang FAN ,  Ming-Hsi YEH ,  Kuo-Bin HUANG

IPC: H01L21/687 ,  H01L21/67 ,  B08B3/08 ,  B08B3/10

Abstract: A method for cleaning a semiconductor wafer is provided. The method includes placing a semiconductor wafer over a supporter arranged around a central axis of a spin base. The method further includes securing the semiconductor wafer using a clamping member positioned on the supporter. The movement of the semiconductor wafer during the placement of the semiconductor wafer over the supporter is guided by a guiding member located over the clamping member. The method also includes spinning the semiconductor wafer by rotating the spin base about the central axis. In addition, the method includes dispensing a processing liquid over the semiconductor wafer.

公开(公告)号：US20190326282A1

公开(公告)日：2019-10-24

申请号：US16404101

申请日：2019-05-06

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ming-Chi HUANG ,  Ying-Liang CHUANG ,  Ming-Hsi YEH ,  Kuo-Bin HUANG

IPC: H01L27/088 ,  H01L29/49 ,  H01L29/423 ,  H01L29/06 ,  H01L29/51 ,  H01L21/311 ,  H01L21/8238 ,  H01L21/3213 ,  H01L21/8234 ,  H01L27/092 ,  H01L29/66

Abstract: Provided is a metal gate structure and related methods that include performing a metal gate cut process. The metal gate cut process includes a plurality of etching steps. For example, a first anisotropic dry etch is performed, a second isotropic dry etch is performed, and a third wet etch is performed. In some embodiments, the second isotropic etch removes a residual portion of a metal gate layer including a metal containing layer. In some embodiments, the third etch removes a residual portion of a dielectric layer.

公开(公告)号：US20190119570A1

公开(公告)日：2019-04-25

申请号：US16220507

申请日：2018-12-14

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Neng-Jye YANG ,  Kuo Bin HUANG ,  Ming-Hsi YEH ,  Shun Wu LIN ,  Yu-Wen WANG ,  Jian-Jou LIAN ,  Shih Min CHANG

IPC: C09K13/02 ,  H01L21/3213 ,  H01L29/66 ,  C09K13/08

Abstract: For a metal gate replacement integration scheme, the present disclosure describes removing a polysilicon gate electrode with a highly selective wet etch chemistry without damaging surrounding layers. For example, the wet etch chemistry can include one or more alkaline solvents with a steric hindrance amine structure, a buffer system that includes tetramethylammonium hydroxide (TMAH) and monoethanolamine (MEA), one or more polar solvents, and water.

公开(公告)号：US20220140107A1

公开(公告)日：2022-05-05

申请号：US17648166

申请日：2022-01-17

Applicant: Taiwan Semiconductor Manufacturing Co.,Ltd.

Inventor： Jian-Jou Lian ,  Chun-Neng LIN ,  Ming-Hsi YEH ,  Chieh-Wei CHEN ,  Tzu-Ang CHIANG

IPC: H01L29/66 ,  H01L21/84 ,  H01L29/78

Abstract: A semiconductor device includes a gate electrode over a channel region of a semiconductor fin, first spacers over the semiconductor fin, and second spacers over the semiconductor fin. A lower portion of the gate electrode is between the first spacers. An upper portion of the gate electrode is above the first spacers. The second spacers are adjacent the first spacers opposite the gate electrode. The upper portion of the gate electrode is between the second spacers.

公开(公告)号：US20190273149A1

公开(公告)日：2019-09-05

申请号：US15909847

申请日：2018-03-01

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ju-Li HUANG ,  Chun-Sheng LIANG ,  Ming-Chi HUANG ,  Ming-Hsi YEH ,  Ying-Liang CHUANG ,  Hsin-Che CHIANG

IPC: H01L29/66 ,  H01L29/78 ,  H01L21/311 ,  H01L21/3213

Abstract: Methods for, and structures formed by, wet process assisted approaches implemented in a replacement gate process are provided. Generally, in some examples, a wet etch process for removing a capping layer can form a first monolayer on the underlying layer as an adhesion layer and a second monolayer on, e.g., an interfacial dielectric layer between a gate spacer and a fin as an etch protection mechanism. Generally, in some examples, a wet process can form a monolayer on a metal layer, like a barrier layer of a work function tuning layer, as a hardmask for patterning of the metal layer.

公开(公告)号：US20190035786A1

公开(公告)日：2019-01-31

申请号：US15799555

申请日：2017-10-31

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ming-Chi HUANG ,  Ying-Liang CHUANG ,  Ming-Hsi YEH ,  Kuo-Bin HUANG

IPC: H01L27/088 ,  H01L21/8234 ,  H01L21/3213 ,  H01L29/49 ,  H01L21/311 ,  H01L29/51 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66

Abstract: Provided is a metal gate structure and related methods that include performing a metal gate cut process. The metal gate cut process includes a plurality of etching steps. For example, a first anisotropic dry etch is performed, a second isotropic dry etch is performed, and a third wet etch is performed. In some embodiments, the second isotropic etch removes a residual portion of a metal gate layer including a metal containing layer. In some embodiments, the third etch removes a residual portion of a dielectric layer.

公开(公告)号：US20210351080A1

公开(公告)日：2021-11-11

申请号：US17168047

申请日：2021-02-04

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chun Hsiung TSAI ,  Yu-Ming LIN ,  Kuo-Feng YU ,  Ming-Hsi YEH ,  Shahaji B. MORE ,  Chandrashekhar Prakash SAVANT ,  Chih-Hsin KO ,  Clement Hsingjen WANN

IPC: H01L21/8234 ,  H01L21/3065 ,  H01L21/306 ,  H01L21/324 ,  H01L21/02

Abstract: In a method of manufacturing a semiconductor device, a fin structure is formed by patterning a semiconductor layer, and an annealing operation is performed on the fin structure. In the patterning of the semiconductor layer, a damaged area is formed on a sidewall of the fin structure, and the annealing operation eliminates the damaged area.

公开(公告)号：US20210202399A1

公开(公告)日：2021-07-01

申请号：US16945595

申请日：2020-07-31

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Cheng-Wei CHANG ,  Chia-Hung CHU ,  Kao-Feng LIN ,  Hsu-Kai CHANG ,  Shuen-Shin LIANG ,  Sung-Li WANG ,  Yi-Ying LIU ,  Po-Nan YEH ,  Yu Shih WANG ,  U-Ting CHIU ,  Chun-Neng LIN ,  Ming-Hsi YEH

IPC: H01L23/532 ,  H01L23/522 ,  H01L21/768

Abstract: A semiconductor device includes a gate electrode, a source/drain structure, a lower contact contacting either of the gate electrode or the source/drain structure, and an upper contact disposed in an opening formed in an interlayer dielectric (ILD) layer and in direct contact with the lower contact. The upper contact is in direct contact with the ILD layer without an interposing conductive barrier layer, and the upper contact includes ruthenium.

公开(公告)号：US20200373298A1

公开(公告)日：2020-11-26

申请号：US16947758

申请日：2020-08-14

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ming-Chi HUANG ,  Ying-Liang CHUANG ,  Ming-Hsi YEH ,  Kuo-Bin HUANG

IPC: H01L27/088 ,  H01L21/3213 ,  H01L21/8234 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L29/49 ,  H01L29/51 ,  H01L29/66 ,  H01L21/311

Abstract: Provided is a metal gate structure and related methods that include performing a metal gate cut process. The metal gate cut process includes a plurality of etching steps. For example, a first anisotropic dry etch is performed, a second isotropic dry etch is performed, and a third wet etch is performed. In some embodiments, the second isotropic etch removes a residual portion of a metal gate layer including a metal containing layer. In some embodiments, the third etch removes a residual portion of a dielectric layer.