公开(公告)号：US20220359741A1

公开(公告)日：2022-11-10

申请号：US17814865

申请日：2022-07-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd,

Inventor： Jian-Jou Lian ,  Chun-Neng Lin ,  Chieh-Wei Chen ,  Tzu-Ang Chiang ,  Ming-Hsi Yeh

IPC: H01L29/78 ,  H01L29/66 ,  H01L21/8238 ,  H01L27/092

Abstract: A method of forming a semiconductor device includes surrounding a dummy gate disposed over a fin with a dielectric material; forming a gate trench in the dielectric material by removing the dummy gate and by removing upper portions of a first gate spacer disposed along sidewalls of the dummy gate, the gate trench comprising a lower trench between remaining lower portions of the first gate spacer and comprising an upper trench above the lower trench; forming a gate dielectric layer, a work function layer and a glue layer successively in the gate trench; removing the glue layer and the work function layer from the upper trench; filling the gate trench with a gate electrode material after the removing; and removing the gate electrode material from the upper trench, remaining portions of the gate electrode material forming a gate electrode.

公开(公告)号：US20240282575A1

公开(公告)日：2024-08-22

申请号：US18638436

申请日：2024-04-17

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jian-Jou Lian ,  Yao-Wen Hsu ,  Neng-Jye Yang ,  Li-Min Chen ,  Chia-Wei Wu ,  Kuan-Lin Chen ,  Kuo-Bin Huang

IPC: H01L21/027 ,  G03F7/09 ,  G03F7/095 ,  G03F7/20 ,  G03F7/32 ,  H01L21/02 ,  H01L21/033 ,  H01L21/306 ,  H01L21/311

CPC classification number: H01L21/0273 ,  G03F7/094 ,  G03F7/20 ,  G03F7/32 ,  H01L21/0228 ,  H01L21/0332 ,  H01L21/0337 ,  H01L21/31111 ,  G03F7/095 ,  H01L21/30608

Abstract: A semiconductor device and method of manufacture are provided. After a patterning of a middle layer, the middle layer is removed. In order to reduce or prevent damage to other underlying layers exposed by the patterning of the middle layer and intervening layers, an inhibitor is included within an etching process in order to inhibit the amount of material removed from the underlying layers.

公开(公告)号：US11942362B2

公开(公告)日：2024-03-26

申请号：US18178948

申请日：2023-03-06

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jian-Jou Lian ,  Kuo-Bin Huang ,  Neng-Jye Yang ,  Li-Min Chen

IPC: H01L21/00 ,  H01L21/02 ,  H01L21/306 ,  H01L21/48 ,  H01L21/768 ,  H01L23/522 ,  H01L23/532

CPC classification number: H01L21/76823 ,  H01L21/02307 ,  H01L21/30604 ,  H01L21/4857 ,  H01L21/76814 ,  H01L21/76826 ,  H01L21/76831 ,  H01L23/5226 ,  H01L23/5329

Abstract: Embodiments described herein relate generally to methods for forming a conductive feature in a dielectric layer in semiconductor processing and structures formed thereby. In some embodiments, a structure includes a dielectric layer over a substrate, a surface modification layer, and a conductive feature. The dielectric layer has a sidewall. The surface modification layer is along the sidewall, and the surface modification layer includes phosphorous and carbon. The conductive feature is along the surface modification layer.

公开(公告)号：US20220334473A1

公开(公告)日：2022-10-20

申请号：US17809912

申请日：2022-06-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Li-Min Chen ,  Kuo Bin Huang ,  Neng-Jye Yang ,  Chia-Wei Wu ,  Jian-Jou Lian

IPC: G03F7/00 ,  G03F7/075 ,  G03F7/09 ,  G03F7/16 ,  H01L21/027 ,  G03F7/42 ,  G03F1/80 ,  H01L21/02 ,  G03F7/20 ,  H01L21/311 ,  H01L21/033 ,  H01L21/768

Abstract: A method includes forming a tri-layer. The tri-layer includes a bottom layer; a middle layer over the bottom layer; and a top layer over the middle layer. The top layer includes a photo resist. The method further includes removing the top layer; and removing the middle layer using a chemical solution. The chemical solution is free from potassium hydroxide (KOH), and includes at least one of a quaternary ammonium hydroxide and a quaternary ammonium fluoride.

公开(公告)号：US11378882B2

公开(公告)日：2022-07-05

申请号：US17007733

申请日：2020-08-31

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Li-Min Chen ,  Kuo Bin Huang ,  Neng-Jye Yang ,  Chia-Wei Wu ,  Jian-Jou Lian

IPC: G03F7/00 ,  G03F7/075 ,  G03F7/09 ,  G03F7/16 ,  H01L21/027 ,  G03F7/42 ,  G03F1/80 ,  H01L21/02 ,  G03F7/20 ,  H01L21/311 ,  H01L21/033 ,  H01L21/768

Abstract: A method includes forming a tri-layer. The tri-layer includes a bottom layer; a middle layer over the bottom layer; and a top layer over the middle layer. The top layer includes a photo resist. The method further includes removing the top layer; and removing the middle layer using a chemical solution. The chemical solution is free from potassium hydroxide (KOH), and includes at least one of a quaternary ammonium hydroxide and a quaternary ammonium fluoride.

公开(公告)号：US20220140107A1

公开(公告)日：2022-05-05

申请号：US17648166

申请日：2022-01-17

Applicant: Taiwan Semiconductor Manufacturing Co.,Ltd.

Inventor： Jian-Jou Lian ,  Chun-Neng LIN ,  Ming-Hsi YEH ,  Chieh-Wei CHEN ,  Tzu-Ang CHIANG

IPC: H01L29/66 ,  H01L21/84 ,  H01L29/78

Abstract: A semiconductor device includes a gate electrode over a channel region of a semiconductor fin, first spacers over the semiconductor fin, and second spacers over the semiconductor fin. A lower portion of the gate electrode is between the first spacers. An upper portion of the gate electrode is above the first spacers. The second spacers are adjacent the first spacers opposite the gate electrode. The upper portion of the gate electrode is between the second spacers.

公开(公告)号：US20240258428A1

公开(公告)日：2024-08-01

申请号：US18630549

申请日：2024-04-09

Applicant: Taiwan Semiconductor Manufacturing Co, Ltd.

Inventor： Jian-Jou Lian ,  Chun-Neng Lin ,  Chieh-Wei Chen ,  Tzu-Ang Chiang ,  Ming-Hsi Yeh

IPC: H01L29/78 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/66

CPC classification number: H01L29/785 ,  H01L21/823821 ,  H01L21/823864 ,  H01L27/0924 ,  H01L29/66545 ,  H01L29/66795

Abstract: A method of forming a semiconductor device includes surrounding a dummy gate disposed over a fin with a dielectric material; forming a gate trench in the dielectric material by removing the dummy gate and by removing upper portions of a first gate spacer disposed along sidewalls of the dummy gate, the gate trench comprising a lower trench between remaining lower portions of the first gate spacer and comprising an upper trench above the lower trench; forming a gate dielectric layer, a work function layer and a glue layer successively in the gate trench; removing the glue layer and the work function layer from the upper trench; filling the gate trench with a gate electrode material after the removing; and removing the gate electrode material from the upper trench, remaining portions of the gate electrode material forming a gate electrode.

公开(公告)号：US20240105818A1

公开(公告)日：2024-03-28

申请号：US18521107

申请日：2023-11-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jian-Jou Lian ,  Chun-Neng Lin ,  Ming-Hsi Yeh ,  Chieh-Wei Chen ,  Tzu-Ang Chiang

IPC: H01L29/66 ,  H01L21/84 ,  H01L29/78

CPC classification number: H01L29/6681 ,  H01L21/845 ,  H01L29/7854

Abstract: A semiconductor device includes a gate electrode over a channel region of a semiconductor fin, first spacers over the semiconductor fin, and second spacers over the semiconductor fin. A lower portion of the gate electrode is between the first spacers. An upper portion of the gate electrode is above the first spacers. The second spacers are adjacent the first spacers opposite the gate electrode. The upper portion of the gate electrode is between the second spacers.

公开(公告)号：US11735426B2

公开(公告)日：2023-08-22

申请号：US17401845

申请日：2021-08-13

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jian-Jou Lian ,  Li-Min Chen ,  Neng-Jye Yang ,  Ming-Hsi Yeh ,  Shun Wu Lin ,  Kuo-Bin Huang

IPC: H01L21/28 ,  H01L29/66 ,  H01L21/3213 ,  H01L21/02 ,  H01L29/08 ,  H01L29/78 ,  H01L29/165 ,  H01L29/267

CPC classification number: H01L21/28247 ,  H01L21/02521 ,  H01L21/02532 ,  H01L21/32134 ,  H01L29/0847 ,  H01L29/165 ,  H01L29/267 ,  H01L29/66545 ,  H01L29/66636 ,  H01L29/66795 ,  H01L29/7848 ,  H01L29/7851

Abstract: An etchant is utilized to remove a semiconductor material. In some embodiments an oxidizer is added to the etchant in order to react with surrounding semiconductor material and form a protective layer. The protective layer is utilized to help prevent damage that could occur from the other components within the etchant.

公开(公告)号：US20220246442A1

公开(公告)日：2022-08-04

申请号：US17722828

申请日：2022-04-18

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jian-Jou Lian ,  Chun-Neng Lin ,  Chieh-Wei Chen ,  Tzu-Ang Chiang ,  Ming-Hsi Yeh

IPC: H01L21/3213 ,  H01L29/51 ,  H01L29/66 ,  H01L21/28 ,  C09K13/00 ,  H01L21/8234

Abstract: In a wet etching process to pattern a metal layer such as a p-metal work function layer over a dielectric layer such as a high-k gate dielectric layer, a selectivity of the wet etching solution between the metal layer and the dielectric layer is increased utilizing an inhibitor. The inhibitor includes such inhibitors as a phosphoric acid, a carboxylic acid, an amino acid, or a hydroxyl group.