公开(公告)号：US20230263069A1

公开(公告)日：2023-08-17

申请号：US17672073

申请日：2022-02-15

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chang-Lin Yang ,  Sheng-Yuan Chang ,  Chung-Te Lin ,  Han-Ting Lin ,  Chien-Hua Huang

IPC: H01L43/08 ,  H01L27/22 ,  H01L43/12 ,  H01L43/02 ,  H01L43/10

CPC classification number: H01L43/08 ,  H01L27/228 ,  H01L43/12 ,  H01L43/02 ,  H01L43/10

Abstract: A method for manufacturing a memory device includes forming a first metal layer over a substrate, forming a magnetic tunnel junction (MTJ) layer stack over the first metal layer, forming a second metal layer over the MTJ layer stack, forming a hard mask layer over the second metal layer, performing a first etching process on the MTJ layer stack to form an MTJ structure and a redeposited layer on a sidewall of the MTJ structure, performing a second etching process to remove the redeposited layer, and performing a third etching process on the sidewall of the MTJ structure.

公开(公告)号：US12048250B2

公开(公告)日：2024-07-23

申请号：US17231357

申请日：2021-04-15

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Chang-Lin Yang ,  Chung-Te Lin ,  Sheng-Yuan Chang ,  Han-Ting Lin ,  Chien-Hua Huang

IPC: H01L43/12 ,  H10B61/00 ,  H10N50/01 ,  H10N50/80

CPC classification number: H10N50/01 ,  H10B61/00 ,  H10N50/80

Abstract: A method for fabricating magnetoresistive random-access memory cells (MRAM) on a substrate is provided. The substrate is formed with a magnetic tunneling junction (MTJ) layer thereon. When the MTJ layer is etched to form the MRAM cells, there may be metal components deposited on a surface of the MRAM cells and between the MRAM cells by chemical reaction. The metal components are then removed by chemical reaction.

公开(公告)号：US12010924B2

公开(公告)日：2024-06-11

申请号：US17205213

申请日：2021-03-18

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chih-Pin Chiu ,  Chang-Lin Yang ,  Chien-Hua Huang ,  Chen-Chiu Huang ,  Chih-Fan Huang ,  Dian-Hau Chen

IPC: H10N50/10 ,  H10B61/00 ,  H10N50/01 ,  H10N50/80 ,  H10N50/85

CPC classification number: H10N50/10 ,  H10B61/00 ,  H10N50/01 ,  H10N50/80 ,  H10N50/85

Abstract: Semiconductor structures and methods for manufacturing the same are provided. The method includes forming a bottom electrode layer over a substrate and forming a pinned layer over the bottom electrode layer. The method also includes forming a tunnel barrier layer over the pinned layer and forming a free layer over the tunnel barrier layer. The method also includes patterning the free layer, the tunnel barrier layer, and the pinned layer to form a magnetic tunnel junction (MTJ) stack structure and patterning the bottom electrode layer to form a bottom electrode structure under the MTJ stack structure. In addition, patterning the free layer includes using a first etching gas, and patterning the bottom electrode layer includes using a second etching gas, which is different from the first etching gas.

公开(公告)号：US20240371953A1

公开(公告)日：2024-11-07

申请号：US18777485

申请日：2024-07-18

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Ming-Yen Chuang ,  Chang-Lin Yang ,  Katherine H. CHIANG ,  Mauricio MANFRINI

IPC: H01L29/417 ,  H01L27/06 ,  H01L29/40 ,  H01L29/423 ,  H01L29/45 ,  H01L29/66 ,  H01L29/786

Abstract: A transistor includes a gate electrode, a gate dielectric layer covering the gate electrode, an active layer covering the gate dielectric layer and including a first metal oxide material, and source/drain electrodes disposed on the active layer and made of a second metal oxide material with an electron concentration of at least about 1018 cm−3. A semiconductor structure and a manufacturing method are also provided.

公开(公告)号：US11849644B2

公开(公告)日：2023-12-19

申请号：US17231320

申请日：2021-04-15

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Chang-Lin Yang ,  Chung-Te Lin ,  Sheng-Yuan Chang ,  Han-Ting Lin ,  Chien-Hua Huang

IPC: H10N50/01 ,  H10B61/00 ,  H10N50/80

CPC classification number: H10N50/01 ,  H10B61/00 ,  H10N50/80

Abstract: A method for fabricating magnetoresistive random-access memory cells (MRAM) on a substrate is provided. The substrate is formed with a magnetic tunneling junction (MTJ) layer thereon. When the MTJ layer is etched to form the MRAM cells, there may be metal components deposited on a surface of the MRAM cells and between the MRAM cells. The metal components are then removed by chemical reaction. However, the removal of the metal components may form extra substances on the substrate. A further etching process is then performed to remove the extra substances by physical etching.

公开(公告)号：US12262642B2

公开(公告)日：2025-03-25

申请号：US18512515

申请日：2023-11-17

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Chang-Lin Yang ,  Chung-Te Lin ,  Sheng-Yuan Chang ,  Han-Ting Lin ,  Chien-Hua Huang

IPC: H10N50/01 ,  H10B61/00 ,  H10N50/80

Abstract: A method for fabricating magnetoresistive random-access memory cells (MRAM) on a substrate is provided. The substrate is formed with a magnetic tunneling junction (MTJ) layer thereon. When the MTJ layer is etched to form the MRAM cells, there may be metal components deposited on a surface of the MRAM cells and between the MRAM cells. The metal components are then removed by chemical reaction. However, the removal of the metal components may form extra substances on the substrate. A further etching process is then performed to remove the extra substances by physical etching.

公开(公告)号：US11211549B1

公开(公告)日：2021-12-28

申请号：US16932639

申请日：2020-07-17

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

Inventor： Chang-Lin Yang ,  Chung-Te Lin ,  Han-Ting Tsai ,  Chien-Hua Huang

IPC: H01L43/02 ,  H01L43/12 ,  H01L27/22

Abstract: An integrated circuit includes a substrate, a dielectric layer over the substrate, a plurality of cells, a plurality of spacers and a plurality of conductive particles. Each of the cells includes a bottom portion in the dielectric layer and an upper portion protruding from the dielectric layer. The spacers are disposed over the dielectric layer and partially cover the upper portions of the cells, respectively. The spacers are disconnected from each other, and cover a first area of the dielectric layer and expose a second area of the dielectric layer. The conductive particles are disposed between the first area of the dielectric layer and the spacers.

公开(公告)号：US12080768B2

公开(公告)日：2024-09-03

申请号：US17407097

申请日：2021-08-19

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Ming-Yen Chuang ,  Chang-Lin Yang ,  Katherine H. Chiang ,  Mauricio Manfrini

IPC: H01L29/417 ,  H01L27/06 ,  H01L29/40 ,  H01L29/423 ,  H01L29/45 ,  H01L29/66 ,  H01L29/786

CPC classification number: H01L29/41775 ,  H01L27/0617 ,  H01L29/401 ,  H01L29/41733 ,  H01L29/41741 ,  H01L29/42384 ,  H01L29/45 ,  H01L29/66742 ,  H01L29/78642 ,  H01L29/7869 ,  H01L2029/42388

Abstract: A transistor includes a gate electrode, a gate dielectric layer covering the gate electrode, an active layer covering the gate dielectric layer and including a first metal oxide material, and source/drain electrodes disposed on the active layer and made of a second metal oxide material with an electron concentration of at least about 1018 cm−3. A semiconductor structure and a manufacturing method are also provided.

公开(公告)号：US20230058626A1

公开(公告)日：2023-02-23

申请号：US17407097

申请日：2021-08-19

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Ming-Yen Chuang ,  Chang-Lin Yang ,  Katherine H. CHIANG ,  Mauricio MANFRINI

IPC: H01L29/417 ,  H01L29/45 ,  H01L29/423 ,  H01L27/06 ,  H01L29/66 ,  H01L29/786 ,  H01L29/40

Abstract: A transistor includes a gate electrode, a gate dielectric layer covering the gate electrode, an active layer covering the gate dielectric layer and including a first metal oxide material, and source/drain electrodes disposed on the active layer and made of a second metal oxide material with an electron concentration of at least about 1018 cm−3. A semiconductor structure and a manufacturing method are also provided.