公开(公告)号：US12262642B2

公开(公告)日：2025-03-25

申请号：US18512515

申请日：2023-11-17

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Chang-Lin Yang ,  Chung-Te Lin ,  Sheng-Yuan Chang ,  Han-Ting Lin ,  Chien-Hua Huang

IPC: H10N50/01 ,  H10B61/00 ,  H10N50/80

Abstract: A method for fabricating magnetoresistive random-access memory cells (MRAM) on a substrate is provided. The substrate is formed with a magnetic tunneling junction (MTJ) layer thereon. When the MTJ layer is etched to form the MRAM cells, there may be metal components deposited on a surface of the MRAM cells and between the MRAM cells. The metal components are then removed by chemical reaction. However, the removal of the metal components may form extra substances on the substrate. A further etching process is then performed to remove the extra substances by physical etching.

公开(公告)号：US20220336727A1

公开(公告)日：2022-10-20

申请号：US17854289

申请日：2022-06-30

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Tai-Yen Peng ,  Hui-Hsien Wei ,  Han-Ting Lin ,  Sin-Yi Yang ,  Yu-Shu Chen ,  An-Shen Chang ,  Qiang Fu ,  Chen-Jung Wang

IPC: H01L43/02 ,  G11C11/16 ,  H01L27/22 ,  H01L43/12

Abstract: In an embodiment, a method includes: forming a first inter-metal dielectric (IMD) layer over a semiconductor substrate; forming a bottom electrode layer over the first IMD layer; forming a magnetic tunnel junction (MTJ) film stack over the bottom electrode layer; forming a first top electrode layer over the MTJ film stack; forming a protective mask covering a first region of the first top electrode layer, a second region of the first top electrode layer being uncovered by the protective mask; forming a second top electrode layer over the protective mask and the first top electrode layer; and patterning the second top electrode layer, the first top electrode layer, the MTJ film stack, the bottom electrode layer, and the first IMD layer with an ion beam etching (IBE) process to form a MRAM cell, where the protective mask is etched during the IBE process.

公开(公告)号：US20230263069A1

公开(公告)日：2023-08-17

申请号：US17672073

申请日：2022-02-15

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chang-Lin Yang ,  Sheng-Yuan Chang ,  Chung-Te Lin ,  Han-Ting Lin ,  Chien-Hua Huang

IPC: H01L43/08 ,  H01L27/22 ,  H01L43/12 ,  H01L43/02 ,  H01L43/10

CPC classification number: H01L43/08 ,  H01L27/228 ,  H01L43/12 ,  H01L43/02 ,  H01L43/10

Abstract: A method for manufacturing a memory device includes forming a first metal layer over a substrate, forming a magnetic tunnel junction (MTJ) layer stack over the first metal layer, forming a second metal layer over the MTJ layer stack, forming a hard mask layer over the second metal layer, performing a first etching process on the MTJ layer stack to form an MTJ structure and a redeposited layer on a sidewall of the MTJ structure, performing a second etching process to remove the redeposited layer, and performing a third etching process on the sidewall of the MTJ structure.

公开(公告)号：US11101429B2

公开(公告)日：2021-08-24

申请号：US16371784

申请日：2019-04-01

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Tai-Yen Peng ,  Sin-Yi Yang ,  Chen-Jung Wang ,  Yu-Shu Chen ,  Chien Chung Huang ,  Han-Ting Lin ,  Jyu-Horng Shieh ,  Chih-Yuan Ting

IPC: H01L43/12 ,  H01L27/22 ,  H01L43/02

Abstract: A method of forming integrated circuits includes forming Magnetic Tunnel Junction (MTJ) stack layers, depositing a conductive etch stop layer over the MTJ stack layers, depositing a conductive hard mask over the conductive etch stop layer, and patterning the conductive hard mask to form etching masks. The patterning is stopped by the conductive etch stop layer. The method further includes etching the conducive etch stop layer using the etching masks to define patterns, and etching the MTJ stack layers to form MTJ stacks.

公开(公告)号：US10862023B2

公开(公告)日：2020-12-08

申请号：US16242689

申请日：2019-01-08

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

Inventor： Tai-Yen Peng ,  Yu-Shu Chen ,  Chien Chung Huang ,  Sin-Yi Yang ,  Chen-Jung Wang ,  Han-Ting Lin ,  Jyu-Horng Shieh ,  Qiang Fu

IPC: H01L29/82 ,  H01L43/02 ,  H01L43/12 ,  H01L43/10

Abstract: The present disclosure provides a semiconductor structure, including a bottom electrode via, a top surface of the bottom electrode via having a first width, a barrier layer surrounding the bottom electrode via, and a magnetic tunneling junction (MTJ) over the bottom electrode via, a bottom of the MTJ having a second width, the first width being narrower than the second width.

公开(公告)号：US12075707B2

公开(公告)日：2024-08-27

申请号：US18358897

申请日：2023-07-25

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

Inventor： Jiann-Horng Lin ,  Kun-Yi Li ,  Han-Ting Lin ,  Huan-Just Lin ,  Chen-Jung Wang ,  Sin-Yi Yang

IPC: H10N50/10 ,  G11C11/16 ,  H10B61/00 ,  H10N50/01 ,  H10N50/80

CPC classification number: H10N50/10 ,  G11C11/161 ,  H10B61/00 ,  H10N50/01 ,  H10N50/80

Abstract: A method for fabricating magnetic tunnel junction (MTJ) pillars is provided. The method includes following operations. A MTJ stack of layers including a first magnetic layer, a tunnel barrier layer overlying the first magnetic layer, and a second magnetic layer overlying the tunnel barrier layer is provided. A first patterning step is carried out by using a reactive ion etching. In the first patterning step, the second magnetic layer and the tunnel barrier layer are etched to form one or more pillar structures and a protection layer is formed and covers sidewalls of the pillar structures.

公开(公告)号：US20240237551A1

公开(公告)日：2024-07-11

申请号：US18615459

申请日：2024-03-25

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Tai-Yen Peng ,  Hui-Hsien Wei ,  Han-Ting Lin ,  Sin-Yi Yang ,  Yu-Shu Chen ,  An-Shen Chang ,  Qiang Fu ,  Chen-Jung Wang

IPC: H10N50/80 ,  G11C11/16 ,  H10B61/00 ,  H10N50/01 ,  H10N50/85

CPC classification number: H10N50/80 ,  G11C11/161 ,  H10B61/20 ,  H10N50/01 ,  G11C11/1655 ,  G11C11/1657 ,  H10N50/85

Abstract: In an embodiment, a method includes: forming a first inter-metal dielectric (IMD) layer over a semiconductor substrate; forming a bottom electrode layer over the first IMD layer; forming a magnetic tunnel junction (MTJ) film stack over the bottom electrode layer; forming a first top electrode layer over the MTJ film stack; forming a protective mask covering a first region of the first top electrode layer, a second region of the first top electrode layer being uncovered by the protective mask; forming a second top electrode layer over the protective mask and the first top electrode layer; and patterning the second top electrode layer, the first top electrode layer, the MTJ film stack, the bottom electrode layer, and the first IMD layer with an ion beam etching (IBE) process to form a MRAM cell, where the protective mask is etched during the IBE process.

公开(公告)号：US20210226118A1

公开(公告)日：2021-07-22

申请号：US16746158

申请日：2020-01-17

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Tai-Yen Peng ,  Hui-Hsien Wei ,  Han-Ting Lin ,  Sin-Yi Yang ,  Yu-Shu Chen ,  An-Shen Chang ,  Qiang Fu ,  Chen-Jung Wang

IPC: H01L43/02 ,  H01L43/12 ,  H01L27/22 ,  G11C11/16

Abstract: In an embodiment, a method includes: forming a first inter-metal dielectric (IMD) layer over a semiconductor substrate; forming a bottom electrode layer over the first IMD layer; forming a magnetic tunnel junction (MTJ) film stack over the bottom electrode layer; forming a first top electrode layer over the MTJ film stack; forming a protective mask covering a first region of the first top electrode layer, a second region of the first top electrode layer being uncovered by the protective mask; forming a second top electrode layer over the protective mask and the first top electrode layer; and patterning the second top electrode layer, the first top electrode layer, the MTJ film stack, the bottom electrode layer, and the first IMD layer with an ion beam etching (IBE) process to form a MRAM cell, where the protective mask is etched during the IBE process.

公开(公告)号：US12048250B2

公开(公告)日：2024-07-23

申请号：US17231357

申请日：2021-04-15

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Chang-Lin Yang ,  Chung-Te Lin ,  Sheng-Yuan Chang ,  Han-Ting Lin ,  Chien-Hua Huang

IPC: H01L43/12 ,  H10B61/00 ,  H10N50/01 ,  H10N50/80

CPC classification number: H10N50/01 ,  H10B61/00 ,  H10N50/80

Abstract: A method for fabricating magnetoresistive random-access memory cells (MRAM) on a substrate is provided. The substrate is formed with a magnetic tunneling junction (MTJ) layer thereon. When the MTJ layer is etched to form the MRAM cells, there may be metal components deposited on a surface of the MRAM cells and between the MRAM cells by chemical reaction. The metal components are then removed by chemical reaction.

公开(公告)号：US11770977B2

公开(公告)日：2023-09-26

申请号：US17081742

申请日：2020-10-27

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

Inventor： Jiann-Horng Lin ,  Kun-Yi Li ,  Han-Ting Lin ,  Huan-Just Lin ,  Chen-Jung Wang ,  Sin-Yi Yang

IPC: H10N50/10 ,  G11C11/16 ,  H10B61/00 ,  H10N50/01 ,  H10N50/80

CPC classification number: H10N50/10 ,  G11C11/161 ,  H10B61/00 ,  H10N50/01 ,  H10N50/80

Abstract: A method for fabricating magnetic tunnel junction (MTJ) pillars is provided. The method includes following operations. A MTJ stack of layers including a first magnetic layer, a tunnel barrier layer overlying the first magnetic layer, and a second magnetic layer overlying the tunnel barrier layer is provided. A first patterning step is carried out by using a reactive ion etching. In the first patterning step, the second magnetic layer and the tunnel barrier layer are etched to form one or more pillar structures and a protection layer is formed and covers sidewalk of the pillar structures.