公开(公告)号：US09478466B2

公开(公告)日：2016-10-25

申请号：US14956071

申请日：2015-12-01

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Hsiu-Jung Yen ,  Jen-Pan Wang

IPC分类号： H01L21/336 ,  H01L21/8234 ,  H01L21/28 ,  H01L29/49 ,  H01L29/66 ,  H01L49/02 ,  H01L27/06 ,  H01L21/306 ,  H01L21/31 ,  H01L21/3205 ,  H01L21/321 ,  H01L21/3213 ,  H01L21/768 ,  H01L21/02 ,  H01L21/311 ,  H01L29/51

CPC分类号： H01L21/8234 ,  H01L21/02164 ,  H01L21/02181 ,  H01L21/02192 ,  H01L21/02271 ,  H01L21/28088 ,  H01L21/30604 ,  H01L21/31 ,  H01L21/31111 ,  H01L21/32051 ,  H01L21/3212 ,  H01L21/32133 ,  H01L21/76895 ,  H01L21/823437 ,  H01L21/823462 ,  H01L21/823468 ,  H01L21/823475 ,  H01L27/0629 ,  H01L28/20 ,  H01L28/24 ,  H01L29/49 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/66583

摘要： A method comprises removing a dummy gate electrode layer to form a gate trench in a dielectric layer over a substrate, forming a resistor trench over the substrate, depositing a plurality of films on a bottom of the gate trench, a bottom of the resistor trench, sidewalls of the gate trench and sidewalls of the resistor trench, depositing a gate electrode layer over the plurality of films and removing an upper portion of the gate electrode layer until the gate electrode layer is removed from the resistor trench.

摘要翻译： 一种方法包括去除伪栅极电极层以在衬底上的电介质层中形成栅极沟槽，在衬底上形成电阻器沟槽，在栅极沟槽的底部沉积多个膜，电阻器沟槽的底部， 栅极沟槽的侧壁和电阻器沟槽的侧壁，在多个膜上沉积栅电极层，并去除栅极电极层的上部，直到栅电极层从电阻沟槽移除。

公开(公告)号：US09093375B2

公开(公告)日：2015-07-28

申请号：US13839631

申请日：2013-03-15

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Hsiu-Jung Yen ,  Jen-Pan Wang

IPC分类号： H01L27/11 ,  H01L21/28 ,  H01L29/49 ,  H01L29/66 ,  H01L49/02 ,  H01L27/06 ,  H01L29/51

CPC分类号： H01L21/8234 ,  H01L21/02164 ,  H01L21/02181 ,  H01L21/02192 ,  H01L21/02271 ,  H01L21/28088 ,  H01L21/30604 ,  H01L21/31 ,  H01L21/31111 ,  H01L21/32051 ,  H01L21/3212 ,  H01L21/32133 ,  H01L21/76895 ,  H01L21/823437 ,  H01L21/823462 ,  H01L21/823468 ,  H01L21/823475 ,  H01L27/0629 ,  H01L28/20 ,  H01L28/24 ,  H01L29/49 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/66583

摘要： A semiconductor structure comprises a metal gate structure formed in a substrate, wherein the metal gate structure comprises a first film formed of a first material and formed on a bottom and sidewalls of a gate trench, a second film formed of a second material and formed over the first film and a gate electrode formed over the second film. The semiconductor structure further comprises a resistor structure formed in the substrate, where the resistor structure comprises a third film formed of the first material and formed on a bottom and sidewalls of a resistor trench and a fourth film formed of the second material and formed over the third film.

摘要翻译： 半导体结构包括形成在衬底中的金属栅极结构，其中金属栅极结构包括由第一材料形成并形成在栅极沟槽的底部和侧壁上的第一膜，由第二材料形成的第二膜， 第一膜和形成在第二膜上的栅电极。 所述半导体结构还包括形成在所述衬底中的电阻器结构，其中所述电阻器结构包括由第一材料形成并形成在电阻器沟槽的底部和侧壁上的第三膜和由第二材料形成的第四膜， 第三部电影。

公开(公告)号：US20140264753A1

公开(公告)日：2014-09-18

申请号：US13935846

申请日：2013-07-05

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Hsiu-Jung Yen ,  Jen-Pan Wang ,  Yu-Hong Pan ,  Chih-Fu Chang

IPC分类号： H01L49/02 ,  H01L21/8234 ,  H01L27/06

CPC分类号： H01L28/20 ,  H01L27/0629 ,  H01L27/0802

摘要： A plurality of openings is formed in a dielectric layer formed on a semiconductor substrate. The plurality of openings comprises a first opening extending to the semiconductor substrate, a second opening extending to a first depth that is substantially less than a thickness of the dielectric layer, and a third opening extending to a second depth that is substantially greater than the first depth. A multi-layer gate electrode is formed in the first opening. A thin resistor structure is formed in the second opening, and a connection structure is formed in the third opening, by filling the second and third openings substantially simultaneously with a resistor metal.

摘要翻译： 在形成于半导体衬底上的电介质层中形成多个开口。 多个开口包括延伸到半导体衬底的第一开口，延伸到基本上小于电介质层的厚度的第一深度的第二开口，以及延伸到第二深度的第三开口，该第二深度基本上大于第一深度 深度。 在第一开口中形成多层栅电极。 在第二开口中形成薄电阻器结构，并且通过基本上与电阻器金属同时地填充第二和第三开口，在第三开口中形成连接结构。

公开(公告)号：US08815679B1

公开(公告)日：2014-08-26

申请号：US13905856

申请日：2013-05-30

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Hsiu-Jung Yen ,  Jen-Pan Wang

IPC分类号： H01L21/8242

CPC分类号： H01L28/75 ,  H01L27/016 ,  H01L27/0629 ,  H01L28/20 ,  H01L28/60

摘要： First and second multi-layer structures are formed within respective openings in at least one dielectric layer formed over a semiconductor substrate. The first multi-layer structure comprises a gate electrode, and the second multi-layer structure comprises a resistor and a first electrode of a metal-insulator-metal (MIM) capacitor structure. The MIM capacitor structure is completed by forming a dielectric film on the at least one dielectric layer and forming a second electrode on the dielectric film.

摘要翻译： 第一和第二多层结构形成在形成在半导体衬底上的至少一个电介质层的相应开口内。 第一多层结构包括栅电极，第二多层结构包括电阻器和金属 - 绝缘体 - 金属（MIM）电容器结构的第一电极。 MIM电容器结构通过在至少一个电介质层上形成电介质膜并在电介质膜上形成第二电极来完成。

公开(公告)号：US09768243B2

公开(公告)日：2017-09-19

申请号：US13935846

申请日：2013-07-05

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Hsiu-Jung Yen ,  Jen-Pan Wang ,  Yu-Hong Pan ,  Chih-Fu Chang

IPC分类号： H01L27/06 ,  H01L49/02 ,  H01L29/66 ,  H01L29/06 ,  H01L27/08

CPC分类号： H01L28/20 ,  H01L27/0629 ,  H01L27/0802

摘要： A plurality of openings is formed in a dielectric layer formed on a semiconductor substrate. The plurality of openings comprises a first opening extending to the semiconductor substrate, a second opening extending to a first depth that is substantially less than a thickness of the dielectric layer, and a third opening extending to a second depth that is substantially greater than the first depth. A multi-layer gate electrode is formed in the first opening. A thin resistor structure is formed in the second opening, and a connection structure is formed in the third opening, by filling the second and third openings substantially simultaneously with a resistor metal.

公开(公告)号：US20140264624A1

公开(公告)日：2014-09-18

申请号：US13839631

申请日：2013-03-15

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Hsiu-Jung Yen ,  Jen-Pan Wang

IPC分类号： H01L29/423 ,  H01L29/40

CPC分类号： H01L21/8234 ,  H01L21/02164 ,  H01L21/02181 ,  H01L21/02192 ,  H01L21/02271 ,  H01L21/28088 ,  H01L21/30604 ,  H01L21/31 ,  H01L21/31111 ,  H01L21/32051 ,  H01L21/3212 ,  H01L21/32133 ,  H01L21/76895 ,  H01L21/823437 ,  H01L21/823462 ,  H01L21/823468 ,  H01L21/823475 ,  H01L27/0629 ,  H01L28/20 ,  H01L28/24 ,  H01L29/49 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/66583

摘要： A semiconductor structure comprises a metal gate structure formed in a substrate, wherein the metal gate structure comprises a first film formed of a first material and formed on a bottom and sidewalls of a gate trench, a second film formed of a second material and formed over the first film and a gate electrode formed over the second film. The semiconductor structure further comprises a resistor structure formed in the substrate, where the resistor structure comprises a third film formed of the first material and formed on a bottom and sidewalls of a resistor trench and a fourth film formed of the second material and formed over the third film.

摘要翻译： 半导体结构包括形成在衬底中的金属栅极结构，其中金属栅极结构包括由第一材料形成并形成在栅极沟槽的底部和侧壁上的第一膜，第二膜由第二材料形成并形成在其上 第一膜和形成在第二膜上的栅电极。 所述半导体结构还包括形成在所述衬底中的电阻器结构，其中所述电阻器结构包括由第一材料形成并形成在电阻器沟槽的底部和侧壁上的第三膜和由第二材料形成的第四膜， 第三部电影。

公开(公告)号：US10686030B2

公开(公告)日：2020-06-16

申请号：US15707271

申请日：2017-09-18

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Hsiu-Jung Yen ,  Jen-Pan Wang ,  Yu-Hong Pan ,  Chih-Fu Chang

IPC分类号： H01L27/08 ,  H01L49/02 ,  H01L27/06

摘要： A plurality of openings is formed in a dielectric layer formed on a semiconductor substrate. The plurality of openings comprises a first opening extending to the semiconductor substrate, a second opening extending to a first depth that is substantially less than a thickness of the dielectric layer, and a third opening extending to a second depth that is substantially greater than the first depth. A multi-layer gate electrode is formed in the first opening. A thin resistor structure is formed in the second opening, and a connection structure is formed in the third opening, by filling the second and third openings substantially simultaneously with a resistor metal.

公开(公告)号：US20180026091A1

公开(公告)日：2018-01-25

申请号：US15707271

申请日：2017-09-18

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Hsiu-Jung Yen ,  Jen-Pan Wang ,  Yu-Hong Pan ,  Chih-Fu Chang

IPC分类号： H01L49/02 ,  H01L27/06 ,  H01L27/08

CPC分类号： H01L28/20 ,  H01L27/0629 ,  H01L27/0802

摘要： A plurality of openings is formed in a dielectric layer formed on a semiconductor substrate. The plurality of openings comprises a first opening extending to the semiconductor substrate, a second opening extending to a first depth that is substantially less than a thickness of the dielectric layer, and a third opening extending to a second depth that is substantially greater than the first depth. A multi-layer gate electrode is formed in the first opening. A thin resistor structure is formed in the second opening, and a connection structure is formed in the third opening, by filling the second and third openings substantially simultaneously with a resistor metal.

公开(公告)号：US20150295060A1

公开(公告)日：2015-10-15

申请号：US14747902

申请日：2015-06-23

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Hsiu-Jung Yen ,  Jen-Pan Wang

IPC分类号： H01L29/49 ,  H01L21/3213 ,  H01L21/306 ,  H01L21/8234 ,  H01L21/3205 ,  H01L21/321 ,  H01L49/02 ,  H01L21/768 ,  H01L29/66 ,  H01L21/31

CPC分类号： H01L21/8234 ,  H01L21/02164 ,  H01L21/02181 ,  H01L21/02192 ,  H01L21/02271 ,  H01L21/28088 ,  H01L21/30604 ,  H01L21/31 ,  H01L21/31111 ,  H01L21/32051 ,  H01L21/3212 ,  H01L21/32133 ,  H01L21/76895 ,  H01L21/823437 ,  H01L21/823462 ,  H01L21/823468 ,  H01L21/823475 ,  H01L27/0629 ,  H01L28/20 ,  H01L28/24 ,  H01L29/49 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/66583

摘要： A method comprises forming a gate trench between a plurality of gate spacers over a substrate, forming a resistor trench over the substrate, depositing a first layer on a bottom of the gate trench, a bottom of the resistor trench, sidewalls of the gate trench and sidewalls of the resistor trench, depositing a second layer over the first layer, depositing a gate electrode layer over the second layer and applying a chemical mechanical polish process to the gate electrode layer until the gate electrode layer is removed from the resistor trench.

摘要翻译： 一种方法包括在衬底上的多个栅极间隔物之间​​形成栅极沟槽，在衬底上形成电阻器沟槽，在栅极沟槽的底部上沉积第一层，电阻沟槽的底部，栅极沟槽的侧壁和 电阻沟槽的侧壁，在第一层上沉积第二层，在第二层上沉积栅极电极层，并向栅极电极层施加化学机械抛光工艺，直到从电阻器沟槽去除栅极电极层。

公开(公告)号：US20160086856A1

公开(公告)日：2016-03-24

申请号：US14956071

申请日：2015-12-01

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Hsiu-Jung Yen ,  Jen-Pan Wang

IPC分类号： H01L21/8234 ,  H01L49/02 ,  H01L21/321 ,  H01L21/311 ,  H01L21/02 ,  H01L29/66 ,  H01L27/06

CPC分类号： H01L21/8234 ,  H01L21/02164 ,  H01L21/02181 ,  H01L21/02192 ,  H01L21/02271 ,  H01L21/28088 ,  H01L21/30604 ,  H01L21/31 ,  H01L21/31111 ,  H01L21/32051 ,  H01L21/3212 ,  H01L21/32133 ,  H01L21/76895 ,  H01L21/823437 ,  H01L21/823462 ,  H01L21/823468 ,  H01L21/823475 ,  H01L27/0629 ,  H01L28/20 ,  H01L28/24 ,  H01L29/49 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/66583

摘要： A method comprises removing a dummy gate electrode layer to form a gate trench in a dielectric layer over a substrate, forming a resistor trench over the substrate, depositing a plurality of films on a bottom of the gate trench, a bottom of the resistor trench, sidewalls of the gate trench and sidewalls of the resistor trench, depositing a gate electrode layer over the plurality of films and removing an upper portion of the gate electrode layer until the gate electrode layer is removed from the resistor trench.

摘要翻译： 一种方法包括去除伪栅极电极层以在衬底上的电介质层中形成栅极沟槽，在衬底上形成电阻器沟槽，在栅极沟槽的底部沉积多个膜，电阻器沟槽的底部， 栅极沟槽的侧壁和电阻器沟槽的侧壁，在多个膜上沉积栅电极层，并去除栅极电极层的上部，直到栅电极层从电阻沟槽移除。