公开(公告)号：US20240387626A1

公开(公告)日：2024-11-21

申请号：US18786260

申请日：2024-07-26

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Kai-Hsuan Lee ,  Shih-Che Lin ,  Po-Yu Huang ,  Shih-Chieh Wu ,  I-Wen Wu ,  Chen-Ming Lee ,  Fu-Kai Yang ,  Mei-Yun Wang

IPC: H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/786

Abstract: A semiconductor device structure includes nanostructures formed over a substrate. The structure also includes a gate structure formed over and around the nanostructures. The structure also includes a spacer layer formed over a sidewall of the gate structure over the nanostructures. The structure also includes a source/drain epitaxial structure formed adjacent to the spacer layer. The structure also includes a contact structure formed over the source/drain epitaxial structure with an air spacer formed between the spacer layer and the contact structure.

公开(公告)号：US20240304689A1

公开(公告)日：2024-09-12

申请号：US18670199

申请日：2024-05-21

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Kai-Hsuan Lee ,  Chen-Ming Lee ,  Fu-Kai Yang ,  Mei-Yun Wang ,  Yen-Ming Chen

IPC: H01L29/417 ,  H01L29/06 ,  H01L29/423 ,  H01L29/51 ,  H01L29/66 ,  H01L29/78 ,  H01L29/786

CPC classification number: H01L29/41775 ,  H01L29/0665 ,  H01L29/42392 ,  H01L29/515 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/7851 ,  H01L29/78696

Abstract: A semiconductor device includes a fin-shape structure protruding from a substrate, a gate stack disposed above the fin-shape structure, an epitaxial feature disposed above the fin-shape structure, and a gate spacer disposed on a sidewall of the gate stack. The gate spacer includes an air gap. The air gap exposes a portion of the epitaxial feature.

公开(公告)号：US20200152522A1

公开(公告)日：2020-05-14

申请号：US16740895

申请日：2020-01-13

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Kai-Hsuan Lee ,  Chia-Ta Yu ,  Cheng-Yu Yang ,  Sheng-Chen Wang ,  Bo-Yu Lai ,  Bo-Cyuan Lu ,  Chi On Chui ,  Sai-Hooi Yeong ,  Feng-Cheng Yang ,  Yen-Ming Chen

IPC: H01L21/8238 ,  H01L29/08 ,  H01L29/49 ,  H01L27/092 ,  H01L29/66 ,  H01L21/8234

Abstract: A method includes forming a gate dielectric layer on a semiconductor fin, and forming a gate electrode over the gate dielectric layer. The gate electrode extends on sidewalls and a top surface of the semiconductor fin. A gate spacer is selectively deposited on a sidewall of the gate electrode. An exposed portion of the gate dielectric layer is free from a same material for forming the gate spacer deposited thereon. The method further includes etching the gate dielectric layer using the gate spacer as an etching mask to expose a portion of the semiconductor fin, and forming an epitaxy semiconductor region based on the semiconductor fin.

公开(公告)号：US11735471B2

公开(公告)日：2023-08-22

申请号：US17225437

申请日：2021-04-08

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chia-Ta Yu ,  Kai-Hsuan Lee ,  Sai-Hooi Yeong ,  Yen-Chieh Huang ,  Feng-Cheng Yang

IPC: H01L21/768 ,  H01L29/78 ,  H01L29/08 ,  H01L29/45 ,  H01L23/532 ,  H01L29/66 ,  H01L21/285 ,  H01L23/535

CPC classification number: H01L21/7682 ,  H01L21/28518 ,  H01L21/76805 ,  H01L21/76843 ,  H01L21/76865 ,  H01L21/76895 ,  H01L23/535 ,  H01L23/5329 ,  H01L29/0847 ,  H01L29/45 ,  H01L29/66795 ,  H01L29/7851

Abstract: A semiconductor structure includes a fin structure formed over a substrate. The structure also includes a gate structure formed across the fin structure. The structure also includes source/drain epitaxial structures formed on opposite sides of the gate structure. The structure also includes an inter-layer dielectric (ILD) structure formed over the gate structure. The structure also includes a contact blocking structure formed through the ILD structure over the source/drain epitaxial structure. A lower portion of the contact blocking structure is surrounded by an air gap, and the air gap is covered by a portion of the ILD structure.

公开(公告)号：US11456383B2

公开(公告)日：2022-09-27

申请号：US16879894

申请日：2020-05-21

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Su-Hao Liu ,  Kuo-Ju Chen ,  Kai-Hsuan Lee ,  I-Hsieh Wong ,  Cheng-Yu Yang ,  Liang-Yin Chen ,  Huicheng Chang ,  Yee-Chia Yeo ,  Syun-Ming Jang ,  Meng-Han Chou

IPC: H01L29/78 ,  H01L29/08 ,  H01L29/417 ,  H01L29/66 ,  H01L29/49 ,  H01L21/3115 ,  H01L21/266 ,  H01L21/8238 ,  H01L21/764 ,  H01L21/768 ,  H01L21/762 ,  H01L21/285

Abstract: A device includes a fin extending from a semiconductor substrate; a gate stack over the fin; a first spacer on a sidewall of the gate stack; a source/drain region in the fin adjacent the first spacer; an inter-layer dielectric layer (ILD) extending over the gate stack, the first spacer, and the source/drain region, the ILD having a first portion and a second portion, wherein the second portion of the ILD is closer to the gate stack than the first portion of the ILD; a contact plug extending through the ILD and contacting the source/drain region; a second spacer on a sidewall of the contact plug; and an air gap between the first spacer and the second spacer, wherein the first portion of the ILD extends across the air gap and physically contacts the second spacer, wherein the first portion of the ILD seals the air gap.

公开(公告)号：US20200287042A1

公开(公告)日：2020-09-10

申请号：US16884805

申请日：2020-05-27

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Kai-Hsuan Lee ,  Bo-Yu Lai ,  Sheng-Chen Wang ,  Sai-Hooi Yeong ,  Yen-Ming Chen ,  Chi On Chui

IPC: H01L29/78 ,  H01L29/66 ,  H01L21/32 ,  H01L21/3105 ,  H01L29/08 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/49 ,  H01L21/321

Abstract: A method includes forming a metal gate in a first inter-layer dielectric, performing a treatment on the metal gate and the first inter-layer dielectric, selectively growing a hard mask on the metal gate without growing the hard mask from the first inter-layer dielectric, depositing a second inter-layer dielectric over the hard mask and the first inter-layer dielectric, planarizing the second inter-layer dielectric and the hard mask, and forming a gate contact plug penetrating through the hard mask to electrically couple to the metal gate.

公开(公告)号：US20190013400A1

公开(公告)日：2019-01-10

申请号：US16105332

申请日：2018-08-20

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Kai-Hsuan Lee ,  Bo-Yu Lai ,  Sheng-Chen Wang ,  Sai-Hooi Yeong ,  Yen-Ming Chen ,  Chi On Chui

IPC: H01L29/78 ,  H01L21/324 ,  H01L21/321 ,  H01L29/66 ,  H01L21/32

Abstract: A method includes forming a metal gate in a first inter-layer dielectric, performing a treatment on the metal gate and the first inter-layer dielectric, selectively growing a hard mask on the metal gate without growing the hard mask from the first inter-layer dielectric, depositing a second inter-layer dielectric over the hard mask and the first inter-layer dielectric, planarizing the second inter-layer dielectric and the hard mask, and forming a gate contact plug penetrating through the hard mask to electrically couple to the metal gate.

公开(公告)号：US20180337100A1

公开(公告)日：2018-11-22

申请号：US16048483

申请日：2018-07-30

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Kai-Hsuan Lee ,  Chia-Ta Yu ,  Cheng-Yu Yang ,  Sheng-Chen Wang ,  Bo-Yu Lai ,  Bo-Cyuan Lu ,  Chi On Chui ,  Sai-Hooi Yeong ,  Feng-Cheng Yang ,  Yen-Ming Chen

IPC: H01L21/8238 ,  H01L29/49 ,  H01L29/08 ,  H01L27/092

Abstract: A method includes forming a gate dielectric layer on a semiconductor fin, and forming a gate electrode over the gate dielectric layer. The gate electrode extends on sidewalls and a top surface of the semiconductor fin. A gate spacer is selectively deposited on a sidewall of the gate electrode. An exposed portion of the gate dielectric layer is free from a same material for forming the gate spacer deposited thereon. The method further includes etching the gate dielectric layer using the gate spacer as an etching mask to expose a portion of the semiconductor fin, and forming an epitaxy semiconductor region based on the semiconductor fin.

公开(公告)号：US12165925B2

公开(公告)日：2024-12-10

申请号：US18354670

申请日：2023-07-19

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Sai-Hooi Yeong ,  Kai-Hsuan Lee ,  Yu-Ming Lin ,  Chi-On Chui

IPC: H01L21/8234 ,  H01L21/308 ,  H01L21/762 ,  H01L21/764 ,  H01L21/768 ,  H01L27/088 ,  H01L29/06 ,  H01L29/66 ,  H01L29/78

Abstract: A method of manufacturing a FinFET includes at last the following steps. A semiconductor substrate is patterned to form trenches in the semiconductor substrate and semiconductor fins located between two adjacent trenches of the trenches. Gate stacks is formed over portions of the semiconductor fins. Strained material portions are formed over the semiconductor fins revealed by the gate stacks. First metal contacts are formed over the gate stacks, the first metal contacts electrically connecting the strained material portions. Air gaps are formed in the FinFET at positions between two adjacent gate stacks and between two adjacent strained materials.

公开(公告)号：US12002863B2

公开(公告)日：2024-06-04

申请号：US17462484

申请日：2021-08-31

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Kai-Hsuan Lee ,  Chen-Ming Lee ,  Fu-Kai Yang ,  Mei-Yun Wang ,  Yen-Ming Chen

IPC: H01L29/417 ,  H01L29/06 ,  H01L29/423 ,  H01L29/51 ,  H01L29/66 ,  H01L29/78 ,  H01L29/786

CPC classification number: H01L29/41775 ,  H01L29/0665 ,  H01L29/42392 ,  H01L29/515 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/7851 ,  H01L29/78696

Abstract: A method includes forming a gate structure on a substrate, forming a seal spacer covering a sidewall of the gate structure, forming a sacrificial spacer covering a sidewall of the seal spacer, forming source/drain regions sandwiching a channel region that is under the gate structure, and depositing a contact etch stop layer covering a sidewall of the sacrificial spacer. The method further includes removing the sacrificial spacer to form a trench, wherein the trench exposes a sidewall of the contact etch stop layer and the sidewall of the seal spacer, and depositing an inter-layer dielectric layer, wherein the inter-layer dielectric layer caps the trench, thereby defining an air gap inside the trench.