利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

19 条记录 (耗时 0.022 秒)

    MEMORY CELL, MEMORY DEVICE AND MANUFACTURING METHOD THEREOF
    1.
    发明公开
    MEMORY CELL, MEMORY DEVICE AND MANUFACTURING METHOD THEREOF 审中-公开

    公开(公告)号：US20230371400A1

    公开(公告)日：2023-11-16

    申请号：US17744732

    申请日：2022-05-16

    申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

    发明人： Kai-Tai Chang ,  Chien-Min Lee ,  Tung-Ying Lee ,  Shy-Jay Lin

    IPC分类号： H01L43/04 ,  H01L27/22 ,  H01L43/06 ,  H01L43/14

    CPC分类号： H01L43/04 ,  H01L27/222 ,  H01L43/06 ,  H01L43/14

    摘要： A memory device and a method of manufacturing the same are provided. The memory device includes a semiconductor substrate, an interconnect structure and a memory cell. The interconnect structure is disposed over the semiconductor substrate, and the memory cell is disposed over the interconnect structure and electrically coupled with the semiconductor substrate and the interconnect structure. The memory cell includes a spin Hall electrode layer, an MTJ pillar, a hard mask, and a spacer. The MTJ pillar is disposed on the spin Hall electrode layer, the hard mask is disposed on the MTJ pillar, and the spacer is disposed on sidewalls of the MTJ pillar and the hard mask. Suitably, the spin Hall electrode layer at least comprises an inner portion and an outer portion surrounding the inner portion, and a top surface of the outer portion is lower than a top surface of the inner portion.

    SEMICONDUCTOR DEVICE STRUCTURE WITH SOURCE/DRAIN STRUCTURE
    3.
    发明申请
    SEMICONDUCTOR DEVICE STRUCTURE WITH SOURCE/DRAIN STRUCTURE 有权

    公开(公告)号：US20220302270A1

    公开(公告)日：2022-09-22

    申请号：US17833373

    申请日：2022-06-06

    申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

    发明人： Tung-Ying Lee ,  Kai-Tai Chang

    IPC分类号： H01L29/417 ,  H01L27/088 ,  H01L21/8234 ,  H01L29/423 ,  H01L29/78 ,  H01L29/06 ,  H01L29/40 ,  H01L29/66

    摘要： A semiconductor device structure is provided. The semiconductor device structure includes a substrate having a base and a fin over the base. The semiconductor device structure includes a gate structure wrapping around a top portion of the fin. The semiconductor device structure includes a first nanostructure over the fin and passing through the gate structure. The semiconductor device structure includes a source/drain structure over the fin. The source/drain structure is over a side of the gate structure and connected to the first nanostructure, the source/drain structure has an upper portion, a lower portion, and a neck portion between the upper portion and the lower portion, the upper portion has a first diamond-like shape, and the lower portion is wider than the neck portion.

    MEMORY CELL, SEMICONDUCTOR DEVICE INCLUDING MEMORY CELL, AND MANUFACTURING METHOD THEREOF
    7.
    发明公开
    MEMORY CELL, SEMICONDUCTOR DEVICE INCLUDING MEMORY CELL, AND MANUFACTURING METHOD THEREOF 审中-公开

    公开(公告)号：US20230337558A1

    公开(公告)日：2023-10-19

    申请号：US18342723

    申请日：2023-06-27

    申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

    发明人： Kai-Tai Chang ,  Tung-Ying Lee

    IPC分类号： H10N70/00 ,  H10B63/00

    CPC分类号： H10N70/882 ,  H10B63/30 ,  H10N70/023

    摘要： A semiconductor device includes a substrate and a memory array disposed over the substrate. The memory array includes at least one film stack disposed over the substrate, a memory layer disposed over the substrate and covering a sidewall and a top of the film stack, a selector layer disposed on the memory layer, and at least one word line disposed on the selector layer and extending transversely with respect to the film stack. The film stack includes conductive layers and insulating layers alternately arranged, each conductive layer includes a first material and a second material in direct contact with each other, and a resistivity value of the second material is lower than a resistivity value of the first material.

    Memory cell, semiconductor device including memory cell, and manufacturing method thereof
    8.
    发明授权
    Memory cell, semiconductor device including memory cell, and manufacturing method thereof 有权

    公开(公告)号：US11785870B2

    公开(公告)日：2023-10-10

    申请号：US17144089

    申请日：2021-01-07

    申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

    发明人： Kai-Tai Chang ,  Tung-Ying Lee

    IPC分类号： H10N70/00 ,  H10B63/00

    CPC分类号： H10N70/882 ,  H10B63/30 ,  H10N70/023

    摘要： A memory cell includes pair of metal layers, insulating layer, memory layer, selector layer, and word line. The pair of metal layers extends in a first direction. A first metal layer of the pair is disposed in contact with a second metal layer of the pair. The first metal layer includes a first material. The second metal layer includes a second material. The second metal layer laterally protrudes with respect to the first metal layer along a second direction perpendicular to the first direction. The insulating layer extends in the first direction and is disposed on top of the pair. The memory layer conformally covers sides of the pair. The selector layer is disposed on the memory layer. The word line extends along the second direction on the selector layer over the pair.

    Reverse tone STI formation
    10.
    发明授权
    Reverse tone STI formation 有权
    反向色STI形成

    公开(公告)号：US08728906B2

    公开(公告)日：2014-05-20

    申请号：US14103397

    申请日：2013-12-11

    申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

    发明人： Kai-Tai Chang ,  Yi-Shan Chen ,  Hsin-Chih Chen ,  Chih-Hsin Ko ,  Clement Hsingjen Wann

    IPC分类号： H01L21/76

    CPC分类号： H01L21/02653 ,  H01L21/02639 ,  H01L21/0337 ,  H01L21/76224 ,  H01L21/76229

    摘要： A method includes forming a hard mask over a substrate, patterning the hard mask to form a first plurality of trenches, and filling a dielectric material into the first plurality of trenches to form a plurality of dielectric regions. The hard mask is removed from between the plurality of dielectric regions, wherein a second plurality of trenches is left by the removed hard mask. An epitaxy step is performed to grow a semiconductor material in the second plurality of trenches.

    摘要翻译： 一种方法包括在衬底上形成硬掩模，图案化硬掩模以形成第一多个沟槽，以及将电介质材料填充到第一多个沟槽中以形成多个电介质区域。 硬掩模从多个电介质区域之间移除，其中第二多个沟槽被去除的硬掩模留下。 进行外延步骤以在第二多个沟槽中生长半导体材料。