公开(公告)号：US11239365B2

公开(公告)日：2022-02-01

申请号：US16726405

申请日：2019-12-24

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Shao-Ming Yu ,  Chang-Yun Chang ,  Chih-Hao Chang ,  Hsin-Chih Chen ,  Kai-Tai Chang ,  Ming-Feng Shieh ,  Kuei-Liang Lu ,  Yi-Tang Lin

IPC分类号： H01L29/78 ,  H01L29/66 ,  H01L21/8234 ,  H01L21/67 ,  H01L27/088

摘要： A semiconductor structure includes an isolation feature formed in the semiconductor substrate and a first fin-type active region. The first fin-type active region extends in a first direction. A dummy gate stack is disposed on an end region of the first fin-type active region. The dummy gate stack may overlie an isolation structure. In an embodiment, any recess such as formed for a source/drain region in the first fin-type active region will be displaced from the isolation region by the distance the dummy gate stack overlaps the first fin-type active region.

公开(公告)号：US11158725B2

公开(公告)日：2021-10-26

申请号：US16511719

申请日：2019-07-15

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Feng Yuan ,  Hung-Ming Chen ,  Tsung-Lin Lee ,  Chang-Yun Chang ,  Clement Hsingjen Wann

IPC分类号： H01L29/66 ,  H01L29/78 ,  H01L21/308 ,  H01L21/3065

摘要： The fin structure includes a first portion and a second, lower portion separated at a transition. The first portion has sidewalls that are substantially perpendicular to the major surface of the substrate. The lower portion has tapered sidewalls on opposite sides of the upper portion and a base having a second width larger than the first width.

公开(公告)号：US20150111355A1

公开(公告)日：2015-04-23

申请号：US14591838

申请日：2015-01-07

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

发明人： Tsung-Lin Lee ,  Chih Chieh Yeh ,  Chang-Yun Chang ,  Feng Yuan

IPC分类号： H01L21/8234 ,  H01L21/762 ,  H01L27/11 ,  H01L21/266

CPC分类号： H01L21/823431 ,  H01L21/266 ,  H01L21/76224 ,  H01L21/823437 ,  H01L21/823481 ,  H01L27/0886 ,  H01L27/1104 ,  H01L27/1116 ,  H01L29/0649 ,  H01L29/41791 ,  H01L29/66795 ,  H01L29/785

摘要： An integrated circuit structure includes a semiconductor substrate including a first portion in a first device region, and a second portion in a second device region. A first semiconductor fin is over the semiconductor substrate and has a first fin height. A second semiconductor fin is over the semiconductor substrate and has a second fin height. The first fin height is greater than the second fin height.

摘要翻译： 集成电路结构包括包括第一器件区域中的第一部分和第二器件区域中的第二部分的半导体衬底。 第一半导体鳍片在半导体衬底之上并且具有第一鳍片高度。 第二半导体鳍片在半导体衬底之上并且具有第二鳍片高度。 第一鳍高度大于第二翅片高度。

公开(公告)号：US20140256107A1

公开(公告)日：2014-09-11

申请号：US14286415

申请日：2014-05-23

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

发明人： Ming-Feng Shieh ,  Chang-Yun Chang ,  Hsin-Chih Chen

IPC分类号： H01L29/66 ,  H01L21/762

CPC分类号： H01L29/66545 ,  H01L21/76224 ,  H01L21/76232 ,  H01L21/823412 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/823481 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823878 ,  H01L29/66636

摘要： A method of forming a semiconductor device includes providing a semiconductor substrate and forming a plurality of dummy gate structures in the substrate. The method further includes forming sidewall spacers on sidewalls of the dummy gate structures and forming a plurality of epitaxial growth regions between the dummy gate structures. After forming the plurality of epitaxial growth regions, one of the dummy gate structures is removed to form an isolation trench, which is filled with a dielectric layer to form an isolation feature. The remaining dummy gate structures are removed to form gate trenches, and gate structures are formed in the gate trenches.

摘要翻译： 形成半导体器件的方法包括提供半导体衬底并在衬底中形成多个虚拟栅极结构。 该方法还包括在虚拟栅极结构的侧壁上形成侧壁间隔物，并在虚拟栅极结构之间形成多个外延生长区域。 在形成多个外延生长区域之后，去除虚拟栅极结构之一以形成隔离沟槽，其中填充有电介质层以形成隔离特征。 去除剩余的虚拟栅极结构以形成栅极沟槽，并且栅极结构形成在栅极沟槽中。

公开(公告)号：US20130313646A1

公开(公告)日：2013-11-28

申请号：US13957108

申请日：2013-08-01

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Ming-Feng Shieh ,  Chih-Hao Yu ,  Chang-Yun Chang

IPC分类号： H01L29/78

CPC分类号： H01L29/7855 ,  H01L21/823431 ,  H01L21/845

摘要： A structure and method of forming a semiconductor device with a fin is provided. In an embodiment a hard mask is utilized to pattern a gate electrode layer and is then removed. After the hard mask has been removed, the gate electrode layer may be separated into individual gate electrodes.

摘要翻译： 提供一种形成具有翅片的半导体器件的结构和方法。 在一个实施例中，使用硬掩模来图案化栅极电极层，然后将其去除。 在硬掩模被去除之后，栅极电极层可以分离成单独的栅电极。

公开(公告)号：US20130280903A1

公开(公告)日：2013-10-24

申请号：US13918311

申请日：2013-06-14

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Jhon-Jhy Liaw ,  Chang-Yun Chang

IPC分类号： H01L27/11

CPC分类号： H01L21/823807 ,  G11C11/412 ,  H01L21/0337 ,  H01L21/3065 ,  H01L21/308 ,  H01L21/3086 ,  H01L21/32139 ,  H01L21/823821 ,  H01L27/11 ,  H01L27/1104 ,  H01L27/1116 ,  H01L29/66545 ,  H01L29/66795

摘要： A system and method for a memory cell layout is disclosed. An embodiment comprises forming dummy layers and spacers along the sidewalls of the dummy layer. Once the spacers have been formed, the dummy layers may be removed and the spacers may be used as a mask. By using the spacers instead of a standard lithographic process, the inherent limitations of the lithographic process can be avoided and further scaling of FinFET devices can be achieved.

摘要翻译： 公开了一种用于存储单元布局的系统和方法。 一个实施例包括沿虚拟层的侧壁形成虚设层和间隔物。 一旦已经形成间隔物，可以去除虚设层，并且间隔物可以用作掩模。 通过使用间隔物而不是标准光刻工艺，可以避免光刻工艺的固有限制，并且可以实现FinFET器件的进一步缩放。

公开(公告)号：US10573751B2

公开(公告)日：2020-02-25

申请号：US15614439

申请日：2017-06-05

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Shao-Ming Yu ,  Chang-Yun Chang ,  Chih-Hao Chang ,  Hsin-Chih Chen ,  Kai-Tai Chang ,  Ming-Feng Shieh ,  Kuei-Liang Lu ,  Yi-Tang Lin

IPC分类号： H01L29/78 ,  H01L29/66 ,  H01L21/8234 ,  H01L21/67 ,  H01L27/088

摘要： A semiconductor structure includes an isolation feature formed in the semiconductor substrate and a first fin-type active region. The first fin-type active region extends in a first direction. A dummy gate stack is disposed on an end region of the first fin-type active region. The dummy gate stack may overlie an isolation structure. In an embodiment, any recess such as formed for a source/drain region in the first fin-type active region will be displaced from the isolation region by the distance the dummy gate stack overlaps the first fin-type active region.

公开(公告)号：US08846465B2

公开(公告)日：2014-09-30

申请号：US13910757

申请日：2013-06-05

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Tsung-Lin Lee ,  Chang-Yun Chang

IPC分类号： H01L21/337 ,  H01L21/762

CPC分类号： H01L21/762 ,  H01L21/76232

摘要： A system and method for forming multi recessed shallow trench isolation structures on substrate of an integrated circuit is provided. An integrated circuit includes a substrate, at least two shallow trench isolation (STI) structures formed in the substrate, an oxide fill disposed in the at least two STI structures, and semiconductor devices disposed on the oxide fill in the at least two STI structures. A first STI structure is formed to a first depth and a second STI structure is formed to a second depth. The oxide fill fills the at least two STI structures, and the first depth and the second depth are based on semiconductor device characteristics of semiconductor devices disposed thereon.

摘要翻译： 提供了一种用于在集成电路的衬底上形成多凹槽浅沟槽隔离结构的系统和方法。 集成电路包括衬底，在衬底中形成的至少两个浅沟槽隔离（STI）结构，设置在至少两个STI结构中的氧化物填充物，以及设置在至少两个STI结构中的氧化物填充物上的半导体器件。 第一STI结构形成为第一深度，并且第二STI结构形成为第二深度。 氧化物填充物填充至少两个STI结构，并且第一深度和第二深度基于设置在其上的半导体器件的半导体器件特性。

公开(公告)号：US08723271B2

公开(公告)日：2014-05-13

申请号：US13918728

申请日：2013-06-14

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Feng Yuan ,  Tsung-Lin Lee ,  Hung-Ming Chen ,  Chang-Yun Chang

IPC分类号： H01L27/02

CPC分类号： H01L27/0203 ,  H01L21/76224 ,  H01L21/764 ,  H01L21/823431 ,  H01L21/823481 ,  H01L21/845

摘要： An integrated circuit structure includes a substrate; two insulation regions over the substrate, with one of the two insulation regions including a void therein; and a first semiconductor strip between and adjoining the two insulation regions. The first semiconductor strip includes a top portion forming a fin over top surfaces of the two insulation regions.

摘要翻译： 集成电路结构包括：基板; 两个绝缘区域在衬底上，两个绝缘区域中的一个在其中包括空隙; 以及在所述两个绝缘区域之间并邻接所述两个绝缘区域的第一半导体条带。 第一半导体条包括在两个绝缘区域的顶表面上形成翅片的顶部部分。

公开(公告)号：US20130267075A1

公开(公告)日：2013-10-10

申请号：US13910757

申请日：2013-06-05

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Tsung-Lin Lee ,  Chang-Yun Chang

IPC分类号： H01L21/762

CPC分类号： H01L21/762 ,  H01L21/76232

摘要： A system and method for forming multi recessed shallow trench isolation structures on substrate of an integrated circuit is provided. An integrated circuit includes a substrate, at least two shallow trench isolation (STI) structures formed in the substrate, an oxide fill disposed in the at least two STI structures, and semiconductor devices disposed on the oxide fill in the at least two STI structures. A first STI structure is formed to a first depth and a second STI structure is formed to a second depth. The oxide fill fills the at least two STI structures, and the first depth and the second depth are based on semiconductor device characteristics of semiconductor devices disposed thereon.

摘要翻译： 提供了一种用于在集成电路的衬底上形成多凹槽浅沟槽隔离结构的系统和方法。 集成电路包括衬底，在衬底中形成的至少两个浅沟槽隔离（STI）结构，设置在至少两个STI结构中的氧化物填充物，以及设置在至少两个STI结构中的氧化物填充物上的半导体器件。 第一STI结构形成为第一深度，并且第二STI结构形成为第二深度。 氧化物填充物填充至少两个STI结构，并且第一深度和第二深度基于设置在其上的半导体器件的半导体器件特性。