公开(公告)号：US20200075742A1

公开(公告)日：2020-03-05

申请号：US16663014

申请日：2019-10-24

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Chia-Hao Chang ,  Ming-Shan Shieh ,  Cheng-Long Chen ,  Chin-Chi Wang ,  Chi-Wen Liu ,  Wai-Yi Lien ,  Chih-Hao Wang

IPC分类号： H01L29/423 ,  H01L21/8238 ,  H01L29/66 ,  H01L29/78 ,  H01L29/775 ,  H01L29/06 ,  B82Y10/00 ,  H01L29/04 ,  H01L29/417 ,  H01L29/08

摘要： Vertical gate all around (VGAA) devices and methods of manufacture thereof are described. A method for manufacturing a VGAA device includes: exposing a top surface and sidewalls of a first portion of a protrusion extending from a doped region, wherein a second portion of the protrusion is surrounded by a gate stack; and enlarging the first portion of the protrusion using an epitaxial growth process.

公开(公告)号：US20160240626A1

公开(公告)日：2016-08-18

申请号：US14660542

申请日：2015-03-17

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Chia-Hao Chang ,  Ming-Shan Shieh ,  Cheng-Long Chen ,  Chin-Chi Wang ,  Chi-Wen Liu ,  Wai-Yi Lien ,  Chih-Hao Wang

IPC分类号： H01L29/423 ,  H01L29/66 ,  H01L21/8238 ,  H01L29/78 ,  H01L21/283 ,  H01L21/02

CPC分类号： H01L29/42392 ,  B82Y10/00 ,  H01L21/823807 ,  H01L21/823885 ,  H01L29/045 ,  H01L29/0676 ,  H01L29/0847 ,  H01L29/41741 ,  H01L29/66439 ,  H01L29/6656 ,  H01L29/66666 ,  H01L29/775 ,  H01L29/7827

摘要： Vertical gate all around (VGAA) devices and methods of manufacture thereof are described. A method for manufacturing a VGAA device includes: exposing a top surface and sidewalls of a first portion of a protrusion extending from a doped region, wherein a second portion of the protrusion is surrounded by a gate stack; and enlarging the first portion of the protrusion using an epitaxial growth process.

摘要翻译： 描述了垂直门（VGAA）装置及其制造方法。 一种用于制造VGAA器件的方法包括：暴露从掺杂区域延伸的突起的第一部分的顶表面和侧壁，其中突起的第二部分被栅极堆叠包围; 并且使用外延生长工艺来扩大突起的第一部分。

公开(公告)号：US10700176B2

公开(公告)日：2020-06-30

申请号：US16663014

申请日：2019-10-24

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Chia-Hao Chang ,  Ming-Shan Shieh ,  Cheng-Long Chen ,  Chin-Chi Wang ,  Chi-Wen Liu ,  Wai-Yi Lien ,  Chih-Hao Wang

IPC分类号： H01L29/423 ,  H01L29/78 ,  H01L29/66 ,  H01L21/8238 ,  H01L29/08 ,  H01L29/06 ,  B82Y10/00 ,  H01L29/04 ,  H01L29/417 ,  H01L29/775

摘要： Vertical gate all around (VGAA) devices and methods of manufacture thereof are described. A method for manufacturing a VGAA device includes: exposing a top surface and sidewalls of a first portion of a protrusion extending from a doped region, wherein a second portion of the protrusion is surrounded by a gate stack; and enlarging the first portion of the protrusion using an epitaxial growth process.

公开(公告)号：US09899489B2

公开(公告)日：2018-02-20

申请号：US14660542

申请日：2015-03-17

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Chia-Hao Chang ,  Ming-Shan Shieh ,  Cheng-Long Chen ,  Chin-Chi Wang ,  Chi-Wen Liu ,  Wai-Yi Lien ,  Chih-Hao Wang

IPC分类号： H01L29/423 ,  H01L29/66 ,  H01L29/78 ,  H01L21/8238 ,  H01L21/283 ,  H01L21/02

CPC分类号： H01L29/42392 ,  B82Y10/00 ,  H01L21/823807 ,  H01L21/823885 ,  H01L29/045 ,  H01L29/0676 ,  H01L29/0847 ,  H01L29/41741 ,  H01L29/66439 ,  H01L29/6656 ,  H01L29/66666 ,  H01L29/775 ,  H01L29/7827

摘要： Vertical gate all around (VGAA) devices and methods of manufacture thereof are described. A method for manufacturing a VGAA device includes: exposing a top surface and sidewalls of a first portion of a protrusion extending from a doped region, wherein a second portion of the protrusion is surrounded by a gate stack; and enlarging the first portion of the protrusion using an epitaxial growth process.

公开(公告)号：US09881922B2

公开(公告)日：2018-01-30

申请号：US15225153

申请日：2016-08-01

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Hong-Lin Chen ,  Shih-Cheng Chen ,  Ming-Shan Shieh ,  Chin-Chi Wang ,  Wai-Yi Lien ,  Chih-Hao Wang

IPC分类号： H01L29/06 ,  H01L27/092 ,  H01L29/66 ,  H01L29/78 ,  H01L29/423 ,  H01L23/544 ,  H01L21/8238 ,  H01L27/088

CPC分类号： H01L27/0924 ,  H01L21/823885 ,  H01L23/544 ,  H01L27/088 ,  H01L27/092 ,  H01L29/0676 ,  H01L29/42356 ,  H01L29/42392 ,  H01L29/66666 ,  H01L29/66742 ,  H01L29/7827 ,  H01L29/785 ,  H01L29/78642 ,  H01L2029/7858 ,  H01L2223/54426 ,  H01L2223/54453 ,  H01L2924/0002 ,  H01L2924/00

摘要： Vertical gate all around devices are formed by initially forming a first doped region and a second doped region that are planar with each other. A channel layer is formed over the first doped region and the second doped region, and a third doped region is formed over the channel layer. A fourth doped region is formed to be planar with the third doped region, and the first doped region, the second doped region, the third doped region, the fourth doped region, and the channel layer are patterned to form a first nanowire and a second nanowire, which are then used to form the vertical gate all around devices.

公开(公告)号：US09431517B2

公开(公告)日：2016-08-30

申请号：US14594001

申请日：2015-01-09

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Hong-Lin Chen ,  Shih-Cheng Chen ,  Ming-Shan Shieh ,  Chin-Chi Wang ,  Wai-Yi Lien ,  Chih-Hao Wang

IPC分类号： H01L21/20 ,  H01L29/66 ,  H01L29/78 ,  H01L29/423 ,  H01L27/088

CPC分类号： H01L27/0924 ,  H01L21/823885 ,  H01L23/544 ,  H01L27/088 ,  H01L27/092 ,  H01L29/0676 ,  H01L29/42356 ,  H01L29/42392 ,  H01L29/66666 ,  H01L29/66742 ,  H01L29/7827 ,  H01L29/785 ,  H01L29/78642 ,  H01L2029/7858 ,  H01L2223/54426 ,  H01L2223/54453 ,  H01L2924/0002 ,  H01L2924/00

摘要： Vertical gate all around devices are formed by initially forming a first doped region and a second doped region that are planar with each other. A channel layer is formed over the first doped region and the second doped region, and a third doped region is formed over the channel layer. A fourth doped region is formed to be planar with the third doped region, and the first doped region, the second doped region, the third doped region, the fourth doped region, and the channel layer are patterned to form a first nanowire and a second nanowire, which are then used to form the vertical gate all around devices.

摘要翻译： 通过初始形成彼此平坦的第一掺杂区域和第二掺杂区域来形成周围器件的垂直栅极。 沟道层形成在第一掺杂区域和第二掺杂区域之上，并且在沟道层上形成第三掺杂区域。 第四掺杂区域形成为与第三掺杂区域平面，并且第一掺杂区域，第二掺杂区域，第三掺杂区域，第四掺杂区域和沟道层被图案化以形成第一纳米线，第二掺杂区域 纳米线，然后用于形成围绕设备的垂直门。

公开(公告)号：US09406780B2

公开(公告)日：2016-08-02

申请号：US14594001

申请日：2015-01-09

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Hong-Lin Chen ,  Shih-Cheng Chen ,  Ming-Shan Shieh ,  Chin-Chi Wang ,  Wai-Yi Lien ,  Chih-Hao Wang

IPC分类号： H01L21/20 ,  H01L29/66 ,  H01L29/78 ,  H01L29/423 ,  H01L27/088

摘要： Vertical gate all around devices are formed by initially forming a first doped region and a second doped region that are planar with each other. A channel layer is formed over the first doped region and the second doped region, and a third doped region is formed over the channel layer. A fourth doped region is formed to be planar with the third doped region, and the first doped region, the second doped region, the third doped region, the fourth doped region, and the channel layer are patterned to form a first nanowire and a second nanowire, which are then used to form the vertical gate all around devices.

公开(公告)号：US20160149019A1

公开(公告)日：2016-05-26

申请号：US14594001

申请日：2015-01-09

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Hong-Lin Chen ,  Shih-Cheng Chen ,  Ming-Shan Shieh ,  Chin-Chi Wang ,  Wai-Yi Lien ,  Chih-Hao Wang

IPC分类号： H01L29/66 ,  H01L29/423 ,  H01L27/088 ,  H01L29/78

CPC分类号： H01L27/0924 ,  H01L21/823885 ,  H01L23/544 ,  H01L27/088 ,  H01L27/092 ,  H01L29/0676 ,  H01L29/42356 ,  H01L29/42392 ,  H01L29/66666 ,  H01L29/66742 ,  H01L29/7827 ,  H01L29/785 ,  H01L29/78642 ,  H01L2029/7858 ,  H01L2223/54426 ,  H01L2223/54453 ,  H01L2924/0002 ,  H01L2924/00

摘要： Vertical gate all around devices are formed by initially forming a first doped region and a second doped region that are planar with each other. A channel layer is formed over the first doped region and the second doped region, and a third doped region is formed over the channel layer. A fourth doped region is formed to be planar with the third doped region, and the first doped region, the second doped region, the third doped region, the fourth doped region, and the channel layer are patterned to form a first nanowire and a second nanowire, which are then used to form the vertical gate all around devices.

公开(公告)号：US10483367B2

公开(公告)日：2019-11-19

申请号：US15872361

申请日：2018-01-16

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Chia-Hao Chang ,  Ming-Shan Shieh ,  Cheng-Long Chen ,  Chin-Chi Wang ,  Chi-Wen Liu ,  Wai-Yi Lien ,  Chih-Hao Wang

IPC分类号： H01L29/423 ,  H01L29/66 ,  H01L29/78 ,  H01L21/8238 ,  H01L21/283 ,  H01L21/02 ,  B82Y10/00 ,  H01L29/417 ,  H01L29/775 ,  H01L29/04 ,  H01L29/06 ,  H01L29/08

摘要： Vertical gate all around (VGAA) devices and methods of manufacture thereof are described. A method for manufacturing a VGAA device includes: exposing a top surface and sidewalls of a first portion of a protrusion extending from a doped region, wherein a second portion of the protrusion is surrounded by a gate stack; and enlarging the first portion of the protrusion using an epitaxial growth process.

公开(公告)号：US20180138282A1

公开(公告)日：2018-05-17

申请号：US15872361

申请日：2018-01-16

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Chia-Hao Chang ,  Ming-Shan Shieh ,  Cheng-Long Chen ,  Chin-Chi Wang ,  Chi-Wen Liu ,  Wai-Yi Lien ,  Chih-Hao Wang

IPC分类号： H01L29/423 ,  H01L29/78 ,  H01L29/66 ,  H01L21/8238

CPC分类号： H01L29/42392 ,  B82Y10/00 ,  H01L21/823807 ,  H01L21/823885 ,  H01L29/045 ,  H01L29/0676 ,  H01L29/0847 ,  H01L29/41741 ,  H01L29/66439 ,  H01L29/6656 ,  H01L29/66666 ,  H01L29/775 ,  H01L29/7827

摘要： Vertical gate all around (VGAA) devices and methods of manufacture thereof are described. A method for manufacturing a VGAA device includes: exposing a top surface and sidewalls of a first portion of a protrusion extending from a doped region, wherein a second portion of the protrusion is surrounded by a gate stack; and enlarging the first portion of the protrusion using an epitaxial growth process.