公开(公告)号：US12009215B2

公开(公告)日：2024-06-11

申请号：US18305074

申请日：2023-04-21

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Chun-Hsiung Lin ,  Jung-Hung Chang ,  Shih-Cheng Chen ,  Kuo-Cheng Chiang ,  Chih-Hao Wang

IPC分类号： H01L29/06 ,  H01L21/285 ,  H01L21/764 ,  H01L29/45 ,  H01L29/66 ,  H01L29/78

CPC分类号： H01L21/28518 ,  H01L21/764 ,  H01L29/0653 ,  H01L29/45 ,  H01L29/6653 ,  H01L29/66795 ,  H01L29/7851 ,  H01L2029/7858

摘要： A semiconductor device structure is provided. The semiconductor device structure includes a substrate having a base portion and a fin portion over the base portion. The semiconductor device structure includes an epitaxial structure over the fin portion. The semiconductor device structure includes a dielectric fin over the base portion. The semiconductor device structure includes a silicide layer between the dielectric fin and the epitaxial structure. A void is between the silicide layer and the dielectric fin.

公开(公告)号：US11967594B2

公开(公告)日：2024-04-23

申请号：US17884840

申请日：2022-08-10

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

发明人： Shih-Cheng Chen ,  Zhi-Chang Lin ,  Jung-Hung Chang ,  Lo Heng Chang ,  Chien Ning Yao ,  Kuo-Cheng Chiang ,  Chih-Hao Wang

IPC分类号： H01L27/092 ,  H01L21/02 ,  H01L21/285 ,  H01L21/8238 ,  H01L29/06 ,  H01L29/423 ,  H01L29/45 ,  H01L29/66 ,  H01L29/786

CPC分类号： H01L27/0922 ,  H01L21/02603 ,  H01L21/28518 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823871 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/45 ,  H01L29/66545 ,  H01L29/66742 ,  H01L29/78618 ,  H01L29/78696

摘要： A semiconductor device structure, along with methods of forming such, are described. The structure includes a stack of semiconductor layers spaced apart from and aligned with each other, a first source/drain epitaxial feature in contact with a first one or more semiconductor layers of the stack of semiconductor layers, and a second source/drain epitaxial feature disposed over the first source/drain epitaxial feature. The second source/drain epitaxial feature is in contact with a second one or more semiconductor layers of the stack of semiconductor layers. The structure further includes a first dielectric material disposed between the first source/drain epitaxial feature and the second source/drain epitaxial feature and a first liner disposed between the first source/drain epitaxial feature and the second source/drain epitaxial feature. The first liner is in contact with the first source/drain epitaxial feature and the first dielectric material.

公开(公告)号：US20230387243A1

公开(公告)日：2023-11-30

申请号：US18446733

申请日：2023-08-09

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Shih-Cheng Chen ,  Kuo-Cheng Chiang ,  Zhi-Chang Lin

IPC分类号： H01L29/49 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/786 ,  H01L21/02

CPC分类号： H01L29/4908 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/4983 ,  H01L29/78618 ,  H01L29/78696 ,  H01L21/02603 ,  H01L29/66553 ,  H01L29/66636 ,  H01L29/66742

摘要： A semiconductor device includes a substrate, a first source/drain feature and a second source/drain feature over the substrate, a first semiconductor layer and a second semiconductor layer between the first and the second source/drain features, and a gate between the first and the second source/drain features. A portion of the gate is further between the first and the second semiconductor layers. Moreover, the semiconductor device includes a first inner spacer and a second inner spacer. The first inner spacer is between the first and the second semiconductor layers and further between the portion of the gate and a portion of the first source/drain feature. Furthermore, the portion of the first source/drain feature is between the first semiconductor layer and the second semiconductor layer. The first inner spacer has a U-shaped profile. Additionally, the second inner spacer is between the first inner spacer and the portion of the first source drain feature.

公开(公告)号：US20230335607A1

公开(公告)日：2023-10-19

申请号：US18211055

申请日：2023-06-16

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

发明人： Jung-Hung Chang ,  Zhi-Chang Lin ,  Shih-Cheng Chen ,  Chien Ning YAO ,  Kuo-Cheng CHIANG ,  Chih-Hao WANG

IPC分类号： H01L29/417 ,  H01L29/06 ,  H01L29/78 ,  H01L21/8234 ,  H01L21/308

CPC分类号： H01L29/41791 ,  H01L29/0665 ,  H01L29/785 ,  H01L21/823412 ,  H01L21/3086 ,  H01L21/823431 ,  H01L2029/7858

摘要： The present disclosure provides a method of forming N-type and P-type source/drain features using one patterned mask and one self-aligned mask to increase windows of error tolerance and provide flexibilities for source/drain features of various shapes and/or volumes. The present disclosure also includes forming a trench between neighboring source/drain features to remove bridging between the neighboring source/drain features. In some embodiments, the trenches between the source/drain features are formed by etching from the backside of the substrate.

公开(公告)号：US20160343713A1

公开(公告)日：2016-11-24

申请号：US15225153

申请日：2016-08-01

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Hong-Lin Chen ,  Shih-Cheng Chen ,  Ming-Shan Shieh ,  Chin-Chi Wang ,  Wai-Yi Lien ,  Chih-Hao Wang

IPC分类号： H01L27/092 ,  H01L29/06 ,  H01L29/78 ,  H01L29/423

CPC分类号： H01L27/0924 ,  H01L21/823885 ,  H01L23/544 ,  H01L27/088 ,  H01L27/092 ,  H01L29/0676 ,  H01L29/42356 ,  H01L29/42392 ,  H01L29/66666 ,  H01L29/66742 ,  H01L29/7827 ,  H01L29/785 ,  H01L29/78642 ,  H01L2029/7858 ,  H01L2223/54426 ,  H01L2223/54453 ,  H01L2924/0002 ,  H01L2924/00

摘要： Vertical gate all around devices are formed by initially forming a first doped region and a second doped region that are planar with each other. A channel layer is formed over the first doped region and the second doped region, and a third doped region is formed over the channel layer. A fourth doped region is formed to be planar with the third doped region, and the first doped region, the second doped region, the third doped region, the fourth doped region, and the channel layer are patterned to form a first nanowire and a second nanowire, which are then used to form the vertical gate all around devices.

摘要翻译： 通过初始形成彼此平坦的第一掺杂区域和第二掺杂区域来形成周围器件的垂直栅极。 沟道层形成在第一掺杂区域和第二掺杂区域之上，并且在沟道层上形成第三掺杂区域。 第四掺杂区域形成为与第三掺杂区域平面，并且第一掺杂区域，第二掺杂区域，第三掺杂区域，第四掺杂区域和沟道层被图案化以形成第一纳米线，第二掺杂区域 纳米线，然后用于形成围绕设备的垂直门。

公开(公告)号：US12107169B2

公开(公告)日：2024-10-01

申请号：US18349354

申请日：2023-07-10

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Zhi-Chang Lin ,  Shih-Cheng Chen ,  Jung-Hung Chang ,  Chien Ning Yao ,  Kuo-Cheng Chiang ,  Chih-Hao Wang

IPC分类号： H01L29/78 ,  H01L21/822 ,  H01L21/8234 ,  H01L27/06 ,  H01L27/092 ,  H01L29/06 ,  H01L29/417 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775 ,  H01L29/786

CPC分类号： H01L29/7855 ,  H01L21/8221 ,  H01L21/823412 ,  H01L21/823418 ,  H01L21/823425 ,  H01L21/823431 ,  H01L21/823475 ,  H01L21/823481 ,  H01L27/0688 ,  H01L27/0922 ,  H01L27/0924 ,  H01L29/0673 ,  H01L29/41733 ,  H01L29/4175 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/775 ,  H01L29/7851 ,  H01L29/78696 ,  H01L2029/7858

摘要： A semiconductor device according to the present disclosure includes a stack of first channel members, a stack of second channel members disposed directly over the stack of first channel members, a bottom source/drain feature in contact with the stack of the first channel members, a separation layer disposed over the bottom source/drain feature, a top source/drain feature in contact with the stack of second channel members and disposed over the separation layer, and a frontside contact that extends through the top source/drain feature and the separation layer to be electrically coupled to the bottom source/drain feature.

公开(公告)号：US11664230B2

公开(公告)日：2023-05-30

申请号：US17397126

申请日：2021-08-09

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Chun-Hsiung Lin ,  Jung-Hung Chang ,  Shih-Cheng Chen ,  Kuo-Cheng Chiang ,  Chih-Hao Wang

IPC分类号： H01L21/285 ,  H01L29/66 ,  H01L29/06 ,  H01L29/45 ,  H01L29/78 ,  H01L21/764

CPC分类号： H01L21/28518 ,  H01L21/764 ,  H01L29/0653 ,  H01L29/45 ,  H01L29/6653 ,  H01L29/66795 ,  H01L29/7851 ,  H01L2029/7858

摘要： A semiconductor device structure is provided. The semiconductor device structure includes a substrate having a base portion and a fin portion over the base portion. The semiconductor device structure includes an epitaxial structure over the fin portion. The semiconductor device structure includes a dielectric fin over the base portion. The semiconductor device structure includes a silicide layer between the dielectric fin and the epitaxial structure. A distance between the silicide layer and the dielectric fin increases toward the base portion.

公开(公告)号：US20220344483A1

公开(公告)日：2022-10-27

申请号：US17238505

申请日：2021-04-23

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

发明人： Jung-Hung Chang ,  Zhi-Chang Lin ,  Shih-Cheng Chen ,  Chien Ning YAO ,  Kuo-Cheng CHIANG ,  CHIH-HAO WANG

IPC分类号： H01L29/417 ,  H01L29/06 ,  H01L29/78 ,  H01L21/8234 ,  H01L21/308

摘要： The present disclosure provides a method of forming N-type and P-type source/drain features using one patterned mask and one self-aligned mask to increase windows of error tolerance and provide flexibilities for source/drain features of various shapes and/or volumes. The present disclosure also includes forming a trench between neighboring source/drain features to remove bridging between the neighboring source/drain features. In some embodiments, the trenches between the source/drain features are formed by etching from the backside of the substrate.

公开(公告)号：US11049774B2

公开(公告)日：2021-06-29

申请号：US16515484

申请日：2019-07-18

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Pei-Hsun Wang ,  Shih-Cheng Chen ,  Chun-Hsiung Lin ,  Chih-Hao Wang

IPC分类号： H01L21/70 ,  H01L21/8238 ,  H01L27/092 ,  H01L21/306 ,  H01L21/3065

摘要： A method includes forming an epitaxy semiconductor layer over a semiconductor substrate, and etching the epitaxy semiconductor layer and the semiconductor substrate to form a semiconductor strip, which includes an upper portion acting as a mandrel, and a lower portion under the mandrel. The upper portion is a remaining portion of the epitaxy semiconductor layer, and the lower portion is a remaining portion of the semiconductor substrate. The method further includes growing a first semiconductor fin starting from a first sidewall of the mandrel, growing a second semiconductor fin starting from a second sidewall of the mandrel. The first sidewall and the second sidewall are opposite sidewalls of the mandrel. A first transistor is formed based on the first semiconductor fin. A second transistor is formed based on the second semiconductor fin.

公开(公告)号：US20240006536A1

公开(公告)日：2024-01-04

申请号：US18349354

申请日：2023-07-10

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Zhi-Chang Lin ,  Shih-Cheng Chen ,  Jung-Hung Chang ,  Chien Ning Yao ,  Kuo-Cheng Chiang ,  Chih-Hao Wang

IPC分类号： H01L29/78 ,  H01L27/092 ,  H01L21/8234 ,  H01L29/66 ,  H01L29/423 ,  H01L29/06 ,  H01L29/786 ,  H01L29/417 ,  H01L27/06

CPC分类号： H01L29/7855 ,  H01L2029/7858 ,  H01L21/823431 ,  H01L21/823412 ,  H01L29/7851 ,  H01L29/66795 ,  H01L21/823418 ,  H01L29/42392 ,  H01L29/0673 ,  H01L29/78696 ,  H01L29/66439 ,  H01L29/66545 ,  H01L29/41733 ,  H01L27/0922 ,  H01L27/0688 ,  H01L27/0924

摘要： A semiconductor device according to the present disclosure includes a stack of first channel members, a stack of second channel members disposed directly over the stack of first channel members, a bottom source/drain feature in contact with the stack of the first channel members, a separation layer disposed over the bottom source/drain feature, a top source/drain feature in contact with the stack of second channel members and disposed over the separation layer, and a frontside contact that extends through the top source/drain feature and the separation layer to be electrically coupled to the bottom source/drain feature.