公开(公告)号：US20240363365A1

公开(公告)日：2024-10-31

申请号：US18769434

申请日：2024-07-11

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Li-Hui Cheng ,  Szu-Wei Lu ,  Ping-Yin Hsieh ,  Chih-Hao Chen

IPC: H01L21/48 ,  H01L21/56 ,  H01L23/00 ,  H01L25/10

CPC classification number: H01L21/486 ,  H01L21/561 ,  H01L24/24 ,  H01L24/25 ,  H01L24/96 ,  H01L25/105 ,  H01L2224/24175 ,  H01L2224/25171 ,  H01L2225/1035 ,  H01L2225/1041 ,  H01L2225/1058

Abstract: A package structure and the manufacturing method thereof are provided. The package structure includes a semiconductor die, conductive through vias, an insulating encapsulant, and a redistribution structure. The conductive through vias are electrically coupled to the semiconductor die. The insulating encapsulant laterally encapsulates the semiconductor die and the conductive through vias, wherein the insulating encapsulant has a recess ring surrounding the semiconductor die, the conductive through vias are located under the recess ring, and a vertical projection of each of the conductive through vias overlaps with a vertical projection of the recess ring. The redistribution structure is electrically connected to the semiconductor die and the conductive through vias.

公开(公告)号：US20230021005A1

公开(公告)日：2023-01-19

申请号：US17738014

申请日：2022-05-06

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Wen-Chih Chiou ,  Ping-Yin Hsieh ,  Ying-Ching Shih ,  Pu Wang ,  Li-Hui Cheng ,  Yi-Huan Liao ,  Chih-Hao Chen

IPC: H01L23/367 ,  H01L21/48 ,  H01L25/065

Abstract: A semiconductor device includes a substrate, a package structure, a thermal interface material (TIM) structure, and a lid structure. The package structure is disposed on the substrate. The TIM structure is disposed on the package structure. The TIM structure includes a metallic TIM layer and a non-metallic TIM layer in contact with the metallic TIM layer, and the non-metallic TIM layer surrounds the metallic TIM layer. The lid structure is disposed on the substrate and the TIM structure.

公开(公告)号：US20240312864A1

公开(公告)日：2024-09-19

申请号：US18676343

申请日：2024-05-28

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Ping-Yin Hsieh ,  Li-Hui Cheng ,  Pu Wang ,  Szu-Wei Lu

IPC: H01L23/367 ,  H01L21/48 ,  H01L21/56 ,  H01L23/00 ,  H01L23/31 ,  H01L23/42 ,  H01L23/498 ,  H01L25/00 ,  H01L25/065

CPC classification number: H01L23/3675 ,  H01L21/4853 ,  H01L21/486 ,  H01L21/4882 ,  H01L21/565 ,  H01L23/3128 ,  H01L23/367 ,  H01L23/42 ,  H01L23/49827 ,  H01L24/16 ,  H01L25/0655 ,  H01L25/50 ,  H01L2224/16235 ,  H01L2924/1715

Abstract: A manufacturing method of a package structure includes: coupling a device package to a package substrate, where the device package includes semiconductor dies encapsulated by an insulating encapsulation and electrically coupled to the package substrate; forming a first dielectric pattern on the device package opposite to the package substrate, where the first dielectric pattern includes openings corresponding to the semiconductor dies of the device package; forming a thermal conductive material on the semiconductor dies of the device package and in the openings of the first dielectric pattern; placing a heat dissipating component over the device package and the package substrate, the heat dissipating component being in contact with the first dielectric pattern and the thermal conductive material; and performing a thermal treatment process on the first dielectric pattern and the thermal conductive material to form a thermal interface material structure coupling the heat dissipating component to the device package.

公开(公告)号：US20220406676A1

公开(公告)日：2022-12-22

申请号：US17351251

申请日：2021-06-18

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Ping-Yin Hsieh ,  Pu Wang ,  Tsung-Fu Tsai ,  Li-Hui Cheng ,  Szu-Wei Lu

IPC: H01L23/367 ,  H01L23/42 ,  H01L23/373 ,  H01L21/52 ,  H01L25/16

Abstract: A semiconductor device includes a substrate, a package structure, a thermal interface material (TIM) layer, and a lid structure. The package structure is disposed on the substrate. The TIM layer is disposed on the package structure. The TIM layer includes a liquid state metal material. The lid structure is disposed on the substrate and the TIM layer. The lid structure includes a trench facing the package structure. At least a portion of the TIM layer is located in the trench.

公开(公告)号：US12033912B2

公开(公告)日：2024-07-09

申请号：US17401296

申请日：2021-08-12

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Ping-Yin Hsieh ,  Li-Hui Cheng ,  Pu Wang ,  Szu-Wei Lu

IPC: H01L23/42 ,  H01L21/48 ,  H01L21/56 ,  H01L23/00 ,  H01L23/31 ,  H01L23/367 ,  H01L23/498 ,  H01L25/00 ,  H01L25/065

CPC classification number: H01L23/3675 ,  H01L21/4853 ,  H01L21/486 ,  H01L21/4882 ,  H01L21/565 ,  H01L23/3128 ,  H01L23/367 ,  H01L23/42 ,  H01L23/49827 ,  H01L24/16 ,  H01L25/0655 ,  H01L25/50 ,  H01L2224/16235 ,  H01L2924/1715

Abstract: A package structure includes first/second/third package components, a thermal interface material (TIM) structure overlying the first package component opposite to the second package component, and a heat dissipating component disposed on the third package component and thermally coupled to the first package component through the TIM structure. The first package component includes semiconductor dies and an insulating encapsulation encapsulating the semiconductor dies, the second package component is interposed between the first and third package components, and the semiconductor dies are electrically coupled to the third package component via the second package component. The TIM structure includes a dielectric dam and thermally conductive members including a conductive material, disposed within areas confined by the dielectric dam, and overlying the semiconductor dies. A manufacturing method of a package structure is also provided.

公开(公告)号：US20230290714A1

公开(公告)日：2023-09-14

申请号：US17693446

申请日：2022-03-14

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Ping-Yin Hsieh ,  Chih-Chien Pan ,  Li-Hui Cheng

IPC: H01L23/498 ,  H01L21/48 ,  H01L25/16

CPC classification number: H01L23/49833 ,  H01L21/4857 ,  H01L21/4853 ,  H01L25/162 ,  H01L23/49822

Abstract: A semiconductor device and a method of manufacturing the same are provided. The semiconductor device includes a first redistribution structure, a packaged device and a second redistribution structure. The packaged device is on a first side of the first redistribution structure and the second redistribution structure is on a second side of the first redistribution structure. An encapsulant is on the second side of the first redistribution structure and laterally around the second redistribution structure, wherein the encapsulant covers a periphery of the second redistribution structure such that an uncovered surface of the second redistribution structure is defined.

公开(公告)号：US20230290650A1

公开(公告)日：2023-09-14

申请号：US18321686

申请日：2023-05-22

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Li-Hui Cheng ,  Szu-Wei Lu ,  Ping-Yin Hsieh ,  Chih-Hao Chen

IPC: H01L21/48 ,  H01L23/00 ,  H01L25/10 ,  H01L21/56

CPC classification number: H01L21/486 ,  H01L24/24 ,  H01L24/25 ,  H01L25/105 ,  H01L24/96 ,  H01L21/561 ,  H01L2224/25171 ,  H01L2225/1035 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2224/24175

Abstract: A package structure and the manufacturing method thereof are provided. The package structure includes a semiconductor die, conductive through vias, an insulating encapsulant, and a redistribution structure. The conductive through vias are electrically coupled to the semiconductor die. The insulating encapsulant laterally encapsulates the semiconductor die and the conductive through vias, wherein the insulating encapsulant has a recess ring surrounding the semiconductor die, the conductive through vias are located under the recess ring, and a vertical projection of each of the conductive through vias overlaps with a vertical projection of the recess ring. The redistribution structure is electrically connected to the semiconductor die and the conductive through vias.

公开(公告)号：US20210358768A1

公开(公告)日：2021-11-18

申请号：US17389193

申请日：2021-07-29

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Li-Hui Cheng ,  Szu-Wei Lu ,  Ping-Yin Hsieh ,  Chih-Hao Chen

IPC: H01L21/48 ,  H01L23/00 ,  H01L25/10 ,  H01L21/56

Abstract: A package structure and the manufacturing method thereof are provided. The package structure includes a semiconductor die, conductive through vias, an insulating encapsulant, and a redistribution structure. The conductive through vias are electrically coupled to the semiconductor die. The insulating encapsulant laterally encapsulates the semiconductor die and the conductive through vias, wherein the insulating encapsulant has a recess ring surrounding the semiconductor die, the conductive through vias are located under the recess ring, and a vertical projection of each of the conductive through vias overlaps with a vertical projection of the recess ring. The redistribution structure is electrically connected to the semiconductor die and the conductive through vias.

公开(公告)号：US20250054824A1

公开(公告)日：2025-02-13

申请号：US18446413

申请日：2023-08-08

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Yi Wen Huang ,  Chih-Hao Chen ,  Ping-Yin Hsieh ,  Yi-Huan Liao ,  Li-Hui Cheng

IPC: H01L23/24 ,  H01L23/367 ,  H01L25/16 ,  H10B80/00

Abstract: A package structure including a packaging substrate, a semiconductor device, passive components, a lid, and a dam structure is provided. The semiconductor device is disposed on and electrically connected to the packaging substrate. The passive components are disposed on the packaging substrate, wherein the semiconductor device is surrounded by the passive components. The lid is disposed on the packaging substrate, and the lid covers the semiconductor device and the passive components. The dam structure is disposed between the packaging substrate and the lid, wherein the dam structure covers the passive components and laterally encloses the semiconductor device.

公开(公告)号：US20240332113A1

公开(公告)日：2024-10-03

申请号：US18193932

申请日：2023-03-31

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Ping-Yin Hsieh ,  Li-Hui Cheng ,  Pu Wang ,  Ying-Ching Shih

IPC: H01L23/367 ,  H01L21/56 ,  H01L23/00 ,  H01L23/31 ,  H01L23/42 ,  H01L23/538 ,  H10B80/00

CPC classification number: H01L23/367 ,  H01L21/56 ,  H01L23/3128 ,  H01L23/42 ,  H01L23/5383 ,  H01L24/29 ,  H01L24/32 ,  H01L24/33 ,  H01L24/83 ,  H10B80/00 ,  H01L2224/26175 ,  H01L2224/29105 ,  H01L2224/29109 ,  H01L2224/29111 ,  H01L2224/29113 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/33181 ,  H01L2224/83439 ,  H01L2224/83444 ,  H01L2224/83447 ,  H01L2224/83455

Abstract: An integrated circuit (IC) device includes a substrate, such as a printed circuit board (PCB) substrate. A chip assembly is disposed over the substrate. The chip assembly includes an IC, a plurality of electronic memory devices coupled to the IC, and a molding compound material that circumferentially surrounds the IC and the electronic memory devices collectively in a top view. A thermal interface material (TIM) is disposed over the chip assembly. The TIM includes an indium alloy, a gallium alloy, or an alloy that contains bismuth, indium, and tin. An adhesive dam is disposed over the substrate. The adhesive dam surrounds the chip assembly and the TIM laterally. A lid structure is disposed over the substrate and encapsulates the chip assembly therein. The lid structure includes one or more openings that expose portions of the TIM. The one or more openings accommodate an expansion of the TIM.