公开(公告)号：US12211818B2

公开(公告)日：2025-01-28

申请号：US18358969

申请日：2023-07-26

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chih-Hao Chen ,  Chih-Chien Pan ,  Pu Wang ,  Li-Hui Cheng ,  Szu-Wei Lu

IPC: H01L23/00 ,  H01L21/48 ,  H01L21/52 ,  H01L21/67 ,  H01L23/40

Abstract: A jig for manufacturing a semiconductor package includes a bottom piece and an upper piece. The bottom piece includes a base, a support plate, and at least one elastic connector. The support plate is located in a central region of the base. The at least one elastic connector is interposed between the support plate and the base. The upper piece includes a cap and outer flanges. The cap overlays the support plate when the upper piece is disposed on the bottom piece. The outer flanges are disposed at edges of the cap, connected with the cap. The outer flanges contact the base of the bottom piece when the upper piece is disposed on the bottom piece. The cap includes an opening which is a through hole. When the upper piece is disposed on the bottom piece, a vertical projection of the opening falls entirely on the support plate.

公开(公告)号：US20230290714A1

公开(公告)日：2023-09-14

申请号：US17693446

申请日：2022-03-14

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Ping-Yin Hsieh ,  Chih-Chien Pan ,  Li-Hui Cheng

IPC: H01L23/498 ,  H01L21/48 ,  H01L25/16

CPC classification number: H01L23/49833 ,  H01L21/4857 ,  H01L21/4853 ,  H01L25/162 ,  H01L23/49822

Abstract: A semiconductor device and a method of manufacturing the same are provided. The semiconductor device includes a first redistribution structure, a packaged device and a second redistribution structure. The packaged device is on a first side of the first redistribution structure and the second redistribution structure is on a second side of the first redistribution structure. An encapsulant is on the second side of the first redistribution structure and laterally around the second redistribution structure, wherein the encapsulant covers a periphery of the second redistribution structure such that an uncovered surface of the second redistribution structure is defined.

公开(公告)号：US11626344B2

公开(公告)日：2023-04-11

申请号：US17580662

申请日：2022-01-21

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chih-Hao Chen ,  Chin-Fu Kao ,  Li-Hui Cheng ,  Szu-Wei Lu ,  Chih-Chien Pan

IPC: H01L23/42 ,  H01L21/56 ,  H01L23/31 ,  H01L23/498 ,  H01L23/538 ,  H01L23/00 ,  H01L27/06 ,  H01L25/065

Abstract: Provided are a package structure and a method of forming the same. The package structure includes a first die, a second die group, an interposer, an underfill layer, a thermal interface material (TIM), and an adhesive pattern. The first die and the second die group are disposed side by side on the interposer. The underfill layer is disposed between the first die and the second die group. The adhesive pattern at least overlay the underfill layer between the first die and the second die group. The TIM has a bottom surface being in direct contact with the first die, the second die group, and the adhesive pattern. The adhesive pattern separates the underfill layer from the TIM.

公开(公告)号：US20220344304A1

公开(公告)日：2022-10-27

申请号：US17242286

申请日：2021-04-27

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chih-Chien Pan ,  Pu Wang ,  Li-Hui Cheng ,  An-Jhih Su ,  Szu-Wei Lu

IPC: H01L25/065 ,  H01L23/00 ,  H01L23/31 ,  H01L23/498

Abstract: A semiconductor structure includes a first semiconductor package, a second semiconductor package, a heat spreader and an underfill layer. The first semiconductor package includes a plurality of lower semiconductor chips and a first dielectric encapsulation layer disposed around the plurality of the lower semiconductor chips. The second semiconductor package is disposed over and corresponds to one of the plurality of lower semiconductor chips, wherein the second semiconductor package includes a plurality of upper semiconductor chips and a second dielectric encapsulation layer disposed around the plurality of upper semiconductor chips. The heat spreader is disposed over and corresponds to another of the plurality of lower semiconductor chips. The underfill layer is disposed over the first semiconductor package and around the second semiconductor package and the heat spreader.

公开(公告)号：US20220139802A1

公开(公告)日：2022-05-05

申请号：US17580662

申请日：2022-01-21

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chih-Hao Chen ,  Chin-Fu Kao ,  Li-Hui Cheng ,  Szu-Wei Lu ,  Chih-Chien Pan

IPC: H01L23/42 ,  H01L23/31 ,  H01L23/00 ,  H01L27/06 ,  H01L21/56

Abstract: Provided are a package structure and a method of forming the same. The package structure includes a first die, a second die group, an interposer, an underfill layer, a thermal interface material (TIM), and an adhesive pattern. The first die and the second die group are disposed side by side on the interposer. The underfill layer is disposed between the first die and the second die group. The adhesive pattern at least overlay the underfill layer between the first die and the second die group. The TIM has a bottom surface being in direct contact with the first die, the second die group, and the adhesive pattern. The adhesive pattern separates the underfill layer from the TIM.

公开(公告)号：US20240282661A1

公开(公告)日：2024-08-22

申请号：US18173033

申请日：2023-02-22

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chih-Chien Pan ,  Yu-Wei Lin ,  Pu Wang ,  Li-Hui Cheng

IPC: H01L23/373 ,  H01L23/00 ,  H01L23/31 ,  H01L23/498 ,  H01L25/07 ,  H01L29/68

CPC classification number: H01L23/373 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/49827 ,  H01L24/16 ,  H01L24/97 ,  H01L25/072 ,  H01L29/685 ,  H01L2224/32225 ,  H01L2224/97 ,  H01L2924/1434

Abstract: A semiconductor package and a manufacturing method thereof are provided. The package includes a substrate, and first, second and third semiconductor elements disposed on and electrically connected to the substrate. A heat transfer enhancing layer, a thermal conductive material layer and an adhesive material layer are respectively disposed on and joined to the first, second and third semiconductor elements. A lid is disposed over the first, second and third semiconductor elements, and joined to the heat transfer enhancing layer, the thermal conductive material layer and the adhesive material layer. The thermal conductive material layer has a thermal conductivity lower than that of the heat transfer enhancing layer and higher than that of the adhesive material layer, and the thermal conductive material layer has a bonding strength larger than that of the heat transfer enhancing layer and smaller than that of the adhesive material layer.

公开(公告)号：US20240234244A1

公开(公告)日：2024-07-11

申请号：US18432061

申请日：2024-02-05

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chih-Hao Chen ,  Chin-Fu Kao ,  Li-Hui Cheng ,  Szu-Wei Lu ,  Chih-Chien Pan

IPC: H01L23/42 ,  H01L21/56 ,  H01L23/00 ,  H01L23/31 ,  H01L23/498 ,  H01L23/538 ,  H01L25/065 ,  H01L27/06

CPC classification number: H01L23/42 ,  H01L21/565 ,  H01L23/3128 ,  H01L23/3157 ,  H01L23/3185 ,  H01L23/49816 ,  H01L23/5386 ,  H01L24/14 ,  H01L24/17 ,  H01L24/27 ,  H01L24/29 ,  H01L25/0655 ,  H01L27/0688 ,  H01L2224/2958

Abstract: Provided are a package structure and a method of forming the same. The package structure includes a first die, a second die group, an interposer, an underfill layer, a thermal interface material (TIM), and an adhesive pattern. The first die and the second die group are disposed side by side on the interposer. The underfill layer is disposed between the first die and the second die group. The adhesive pattern at least overlay the underfill layer between the first die and the second die group. The TIM has a bottom surface being in direct contact with the first die, the second die group, and the adhesive pattern. The adhesive pattern separates the underfill layer from the TIM.

公开(公告)号：US20230378130A1

公开(公告)日：2023-11-23

申请号：US18351478

申请日：2023-07-12

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chih-Chien Pan ,  Pu Wang ,  Li-Hui Cheng ,  An-Jhih Su ,  Szu-Wei Lu

IPC: H01L25/065 ,  H01L23/00 ,  H01L23/498 ,  H01L23/31

CPC classification number: H01L25/0652 ,  H01L24/27 ,  H01L23/49816 ,  H01L24/33 ,  H01L23/3135 ,  H01L24/32 ,  H01L2224/33519 ,  H01L24/48 ,  H01L2224/48225 ,  H01L2224/33517 ,  H01L2224/32145

Abstract: A semiconductor structure includes a first semiconductor package, a second semiconductor package, a heat spreader and an dielectric layer. The first semiconductor package includes a plurality of first semiconductor chips and a first dielectric encapsulation layer disposed around the plurality of the first semiconductor chips. The second semiconductor package is disposed over and corresponds to one of the plurality of first semiconductor chips, wherein the second semiconductor package includes a plurality of second semiconductor chips and a second dielectric encapsulation layer disposed around the plurality of second semiconductor chips. The heat spreader is disposed over and corresponds to another of the plurality of first semiconductor chips. The dielectric layer is disposed over the first semiconductor package and around the second semiconductor package and the heat spreader.

公开(公告)号：US11742323B2

公开(公告)日：2023-08-29

申请号：US17242286

申请日：2021-04-27

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chih-Chien Pan ,  Pu Wang ,  Li-Hui Cheng ,  An-Jhih Su ,  Szu-Wei Lu

IPC: H01L25/065 ,  H01L23/00 ,  H01L23/31 ,  H01L23/498

CPC classification number: H01L25/0652 ,  H01L23/3135 ,  H01L23/49816 ,  H01L24/27 ,  H01L24/32 ,  H01L24/33 ,  H01L24/48 ,  H01L2224/32145 ,  H01L2224/33517 ,  H01L2224/33519 ,  H01L2224/48225

Abstract: A semiconductor structure includes a first semiconductor package, a second semiconductor package, a heat spreader and an underfill layer. The first semiconductor package includes a plurality of lower semiconductor chips and a first dielectric encapsulation layer disposed around the plurality of the lower semiconductor chips. The second semiconductor package is disposed over and corresponds to one of the plurality of lower semiconductor chips, wherein the second semiconductor package includes a plurality of upper semiconductor chips and a second dielectric encapsulation layer disposed around the plurality of upper semiconductor chips. The heat spreader is disposed over and corresponds to another of the plurality of lower semiconductor chips. The underfill layer is disposed over the first semiconductor package and around the second semiconductor package and the heat spreader.

公开(公告)号：US11664286B2

公开(公告)日：2023-05-30

申请号：US17372814

申请日：2021-07-12

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chih-Hao Chen ,  Chih-Chien Pan ,  Li-Hui Cheng ,  Chin-Fu Kao ,  Szu-Wei Lu

IPC: H01L23/18 ,  H01L23/498 ,  H01L23/31 ,  H01L21/56 ,  H01L23/00

CPC classification number: H01L23/18 ,  H01L21/565 ,  H01L23/3185 ,  H01L23/49816 ,  H01L24/81

Abstract: A method for forming a package structure is provided. The method for forming a package structure includes bonding a package component to a first surface of a substrate through a plurality of first connectors. The package component includes a first semiconductor die and a second semiconductor die. The method also includes forming a dam structure over the first surface of the substrate. The dam structure is around and separated from the package component, and a top surface of the dam structure is higher than a top surface of the package component. The method further includes forming an underfill layer between the dam structure and the package component. In addition, the method includes removing the dam structure after the underfill layer is formed.