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    Ultra high voltage electrostatic discharge protection device with current gain
    1.
    发明授权
    Ultra high voltage electrostatic discharge protection device with current gain 有权
    具有电流增益的超高压静电放电保护装置

    公开(公告)号：US09379179B2

    公开(公告)日：2016-06-28

    申请号：US14079715

    申请日：2013-11-14

    申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

    发明人： Hsin-Chih Chiang ,  Tung-Yang Lin ,  Ruey-Hsin Liu ,  Ming-Ta Lei

    IPC分类号： H01L29/06 ,  H01L29/66 ,  H01L29/861 ,  H01L27/02

    CPC分类号： H01L27/0255 ,  H01L29/0619 ,  H01L29/0623 ,  H01L29/063 ,  H01L29/66121 ,  H01L29/861

    摘要： A semiconductor device configured to provide increased current gain comprises a semiconductor substrate having a first conductivity type. The device also comprises a first semiconductor region having a second conductivity type. The device further comprises a second semiconductor region in the first semiconductor region to having the first conductivity type. The device additionally comprises a third semiconductor region in the first semiconductor region having the second conductivity type. The device also comprises a fourth semiconductor region outside the first semiconductor region having the first conductivity type. The device further comprises a fifth semiconductor region outside the first semiconductor region adjacent the fourth semiconductor region and having the second conductivity type. The device additionally comprises a first electrode electrically connected to the third semiconductor region. The device further comprises a second electrode electrically connected to the fourth semiconductor region and to the fifth semiconductor region.

    摘要翻译： 配置成提供增加的电流增益的半导体器件包括具有第一导电类型的半导体衬底。 该器件还包括具有第二导电类型的第一半导体区域。 该器件还包括在第一半导体区域中具有第一导电类型的第二半导体区域。 该器件还包括具有第二导电类型的第一半导体区域中的第三半导体区域。 该器件还包括具有第一导电类型的第一半导体区域之外的第四半导体区域。 该器件还包括与第四半导体区域相邻并具有第二导电类型的第一半导体区域外的第五半导体区域。 该装置还包括电连接到第三半导体区域的第一电极。 该器件还包括电连接到第四半导体区域和第五半导体区域的第二电极。

    Power MOSFETs and methods for forming the same
    3.
    发明授权
    Power MOSFETs and methods for forming the same 有权
    功率MOSFET及其形成方法

    公开(公告)号：US09000517B2

    公开(公告)日：2015-04-07

    申请号：US13739024

    申请日：2013-01-11

    申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

    发明人： Fu-Yu Chu ,  Chih-Chang Cheng ,  Tung-Yang Lin ,  Ruey-Hsin Liu

    IPC分类号： H01L29/78 ,  H01L27/092 ,  H01L29/66 ,  H01L21/265

    CPC分类号： H01L29/7823 ,  H01L21/26513 ,  H01L21/26586 ,  H01L21/266 ,  H01L29/0847 ,  H01L29/0865 ,  H01L29/0878 ,  H01L29/0882 ,  H01L29/1045 ,  H01L29/1095 ,  H01L29/402 ,  H01L29/66659 ,  H01L29/66681 ,  H01L29/7816 ,  H01L29/7835

    摘要： Power Metal-Oxide-Semiconductor Field-Effect Transistors (MOSFETs) and methods of forming the same are provided. A power MOSFET may comprise a first drift region formed at a side of a gate electrode, and a second drift region beneath the gate electrode, adjacent to the first drift region, with a depth less than a depth of the first drift region so that the first drift region and the second drift region together form a stepwise shape. A sum of a depth of the second drift region, a depth of the gate dielectric, and a depth of the gate electrode may be of substantially a same value as a depth of the first drift region. The first drift region and the second drift region may be formed at the same time, using the gate electrode as a part of the implanting mask.

    摘要翻译： 功率金属氧化物半导体场效应晶体管（MOSFET）及其形成方法。 功率MOSFET可以包括形成在栅极侧的第一漂移区域和与第一漂移区域相邻的栅电极下方的第二漂移区域，其深度小于第一漂移区域的深度，使得 第一漂移区域和第二漂移区域一起形成阶梯形状。 第二漂移区域的深度，栅极电介质的深度和栅电极的深度之和可以与第一漂移区域的深度基本相同。 可以使用栅电极作为植入掩模的一部分，同时形成第一漂移区域和第二漂移区域。

    Power MOSFETs and Methods for Forming the Same
    4.
    发明申请
    Power MOSFETs and Methods for Forming the Same 有权
    功率MOSFET及其形成方法

    公开(公告)号：US20140197489A1

    公开(公告)日：2014-07-17

    申请号：US13739024

    申请日：2013-01-11

    申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

    发明人： Fu-Yu Chu ,  Chih-Chang Cheng ,  Tung-Yang Lin ,  Ruey-Hsin Liu

    IPC分类号： H01L29/78 ,  H01L29/66

    CPC分类号： H01L29/7823 ,  H01L21/26513 ,  H01L21/26586 ,  H01L21/266 ,  H01L29/0847 ,  H01L29/0865 ,  H01L29/0878 ,  H01L29/0882 ,  H01L29/1045 ,  H01L29/1095 ,  H01L29/402 ,  H01L29/66659 ,  H01L29/66681 ,  H01L29/7816 ,  H01L29/7835

    摘要： Power Metal-Oxide-Semiconductor Field-Effect Transistors (MOSFETs) and methods of forming the same are provided. A power MOSFET may comprise a first drift region formed at a side of a gate electrode, and a second drift region beneath the gate electrode, adjacent to the first drift region, with a depth less than a depth of the first drift region so that the first drift region and the second drift region together form a stepwise shape. A sum of a depth of the second drift region, a depth of the gate dielectric, and a depth of the gate electrode may be of substantially a same value as a depth of the first drift region. The first drift region and the second drift region may be formed at the same time, using the gate electrode as a part of the implanting mask.

    摘要翻译： 功率金属氧化物半导体场效应晶体管（MOSFET）及其形成方法。 功率MOSFET可以包括形成在栅极侧的第一漂移区域和与第一漂移区域相邻的栅电极下方的第二漂移区域，其深度小于第一漂移区域的深度，使得 第一漂移区域和第二漂移区域一起形成阶梯形状。 第二漂移区域的深度，栅极电介质的深度和栅电极的深度之和可以与第一漂移区域的深度基本相同。 可以使用栅电极作为植入掩模的一部分，同时形成第一漂移区域和第二漂移区域。

    BREAKDOWN VOLTAGE CAPABILITY OF HIGH VOLTAGE DEVICE
    6.
    发明申请
    BREAKDOWN VOLTAGE CAPABILITY OF HIGH VOLTAGE DEVICE 有权

    公开(公告)号：US20230014120A1

    公开(公告)日：2023-01-19

    申请号：US17949266

    申请日：2022-09-21

    申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

    发明人： Hsin-Chih Chiang ,  Tung-Yang Lin ,  Ruey-Hsin Liu ,  Ming-Ta Lei

    IPC分类号： H01L27/12 ,  H01L21/74 ,  H01L21/84 ,  H01L23/48 ,  H01L21/768 ,  H01L29/06 ,  H01L29/10 ,  H01L21/762 ,  H01L29/423

    摘要： Various embodiments of the present disclosure are directed towards an integrated chip. The integrated chip includes a semiconductor substrate having a device substrate overlying a handle substrate and an insulator layer disposed between the device substrate and the handle substrate. A gate electrode overlies the device substrate between a drain region and a source region. A conductive via extends through the device substrate and the insulator layer to contact the handle substrate. A first isolation structure is disposed within the device substrate and comprises a first isolation segment disposed laterally between the gate electrode and the conductive via. A contact region is disposed within the device substrate between the first isolation segment and the conductive via. A conductive gate electrode directly overlies the first isolation segment and is electrically coupled to the contact region.

    Semiconductor device having drain side contact through buried oxide
    10.
    发明授权
    Semiconductor device having drain side contact through buried oxide 有权
    具有通过埋入氧化物的漏极侧接触的半导体器件

    公开(公告)号：US09431531B2

    公开(公告)日：2016-08-30

    申请号：US14089803

    申请日：2013-11-26

    申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

    发明人： Tung-Yang Lin ,  Hsin-Chih Chiang ,  Ruey-Hsin Liu ,  Ming-Ta Lei

    IPC分类号： H01L29/78 ,  H01L21/74 ,  H01L29/786 ,  H01L29/10

    CPC分类号： H01L29/7824 ,  H01L21/743 ,  H01L29/1087 ,  H01L29/78624

    摘要： A semiconductor device configured to provide high heat dissipation and improve breakdown voltage comprises a substrate, a buried oxide layer over the substrate, a buried n+ region in the substrate below the buried oxide layer, and an epitaxial layer over the buried oxide layer. The epitaxial layer comprises a p-well, an n-well, and a drift region between the p-well and the n-well. The semiconductor device also comprises a source contact, a first electrode electrically connecting the source contact to the p-well, and a gate over a portion of the p-well and a portion of the drift region. The semiconductor device further comprises a drain contact, and a second electrode extending from the drain contact through the n-well and through the buried oxide layer to the buried n+ region. The second electrode electrically connects the drain contact to the n-well and to the buried n+ region.

    摘要翻译： 配置为提供高散热并改善击穿电压的半导体器件包括衬底，衬底上的掩埋氧化物层，掩埋氧化物层下面的衬底中的掩埋的n +区，以及在掩埋氧化物层上的外延层。 外延层包括p阱，n阱以及p阱和n阱之间的漂移区。 半导体器件还包括源极接触，将源极接触电连接到p阱的第一电极以及p阱的一部分和漂移区的一部分上的栅极。 半导体器件还包括漏极接触，以及从漏极接触通过n阱延伸并穿过掩埋氧化物层到掩埋的n +区域的第二电极。 第二电极将漏极接触电连接到n阱和掩埋的n +区域。