公开(公告)号：US09379179B2

公开(公告)日：2016-06-28

申请号：US14079715

申请日：2013-11-14

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Hsin-Chih Chiang ,  Tung-Yang Lin ,  Ruey-Hsin Liu ,  Ming-Ta Lei

IPC: H01L29/06 ,  H01L29/66 ,  H01L29/861 ,  H01L27/02

CPC classification number: H01L27/0255 ,  H01L29/0619 ,  H01L29/0623 ,  H01L29/063 ,  H01L29/66121 ,  H01L29/861

Abstract: A semiconductor device configured to provide increased current gain comprises a semiconductor substrate having a first conductivity type. The device also comprises a first semiconductor region having a second conductivity type. The device further comprises a second semiconductor region in the first semiconductor region to having the first conductivity type. The device additionally comprises a third semiconductor region in the first semiconductor region having the second conductivity type. The device also comprises a fourth semiconductor region outside the first semiconductor region having the first conductivity type. The device further comprises a fifth semiconductor region outside the first semiconductor region adjacent the fourth semiconductor region and having the second conductivity type. The device additionally comprises a first electrode electrically connected to the third semiconductor region. The device further comprises a second electrode electrically connected to the fourth semiconductor region and to the fifth semiconductor region.

Abstract translation: 配置成提供增加的电流增益的半导体器件包括具有第一导电类型的半导体衬底。 该器件还包括具有第二导电类型的第一半导体区域。 该器件还包括在第一半导体区域中具有第一导电类型的第二半导体区域。 该器件还包括具有第二导电类型的第一半导体区域中的第三半导体区域。 该器件还包括具有第一导电类型的第一半导体区域之外的第四半导体区域。 该器件还包括与第四半导体区域相邻并具有第二导电类型的第一半导体区域外的第五半导体区域。 该装置还包括电连接到第三半导体区域的第一电极。 该器件还包括电连接到第四半导体区域和第五半导体区域的第二电极。

公开(公告)号：US11456380B2

公开(公告)日：2022-09-27

申请号：US15464737

申请日：2017-03-21

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

Inventor： Tung-Yang Lin ,  Hsueh-Liang Chou

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/40

Abstract: Present disclosure provides a transistor structure, including a substrate, a first gate over the substrate, a second gate over the substrate and laterally in contact with the first gate, a first conductive region of a first conductivity type in the substrate, self-aligning to a side of the first gate, and a second conductive region of the first conductivity type in the substrate, self-aligning to a side of the second gate. A method for manufacturing the transistor structure is also disclosed.

公开(公告)号：US09000517B2

公开(公告)日：2015-04-07

申请号：US13739024

申请日：2013-01-11

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Fu-Yu Chu ,  Chih-Chang Cheng ,  Tung-Yang Lin ,  Ruey-Hsin Liu

IPC: H01L29/78 ,  H01L27/092 ,  H01L29/66 ,  H01L21/265

CPC classification number: H01L29/7823 ,  H01L21/26513 ,  H01L21/26586 ,  H01L21/266 ,  H01L29/0847 ,  H01L29/0865 ,  H01L29/0878 ,  H01L29/0882 ,  H01L29/1045 ,  H01L29/1095 ,  H01L29/402 ,  H01L29/66659 ,  H01L29/66681 ,  H01L29/7816 ,  H01L29/7835

Abstract: Power Metal-Oxide-Semiconductor Field-Effect Transistors (MOSFETs) and methods of forming the same are provided. A power MOSFET may comprise a first drift region formed at a side of a gate electrode, and a second drift region beneath the gate electrode, adjacent to the first drift region, with a depth less than a depth of the first drift region so that the first drift region and the second drift region together form a stepwise shape. A sum of a depth of the second drift region, a depth of the gate dielectric, and a depth of the gate electrode may be of substantially a same value as a depth of the first drift region. The first drift region and the second drift region may be formed at the same time, using the gate electrode as a part of the implanting mask.

Abstract translation: 功率金属氧化物半导体场效应晶体管（MOSFET）及其形成方法。 功率MOSFET可以包括形成在栅极侧的第一漂移区域和与第一漂移区域相邻的栅电极下方的第二漂移区域，其深度小于第一漂移区域的深度，使得 第一漂移区域和第二漂移区域一起形成阶梯形状。 第二漂移区域的深度，栅极电介质的深度和栅电极的深度之和可以与第一漂移区域的深度基本相同。 可以使用栅电极作为植入掩模的一部分，同时形成第一漂移区域和第二漂移区域。

公开(公告)号：US20140197489A1

公开(公告)日：2014-07-17

申请号：US13739024

申请日：2013-01-11

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Fu-Yu Chu ,  Chih-Chang Cheng ,  Tung-Yang Lin ,  Ruey-Hsin Liu

IPC: H01L29/78 ,  H01L29/66

CPC classification number: H01L29/7823 ,  H01L21/26513 ,  H01L21/26586 ,  H01L21/266 ,  H01L29/0847 ,  H01L29/0865 ,  H01L29/0878 ,  H01L29/0882 ,  H01L29/1045 ,  H01L29/1095 ,  H01L29/402 ,  H01L29/66659 ,  H01L29/66681 ,  H01L29/7816 ,  H01L29/7835

Abstract: Power Metal-Oxide-Semiconductor Field-Effect Transistors (MOSFETs) and methods of forming the same are provided. A power MOSFET may comprise a first drift region formed at a side of a gate electrode, and a second drift region beneath the gate electrode, adjacent to the first drift region, with a depth less than a depth of the first drift region so that the first drift region and the second drift region together form a stepwise shape. A sum of a depth of the second drift region, a depth of the gate dielectric, and a depth of the gate electrode may be of substantially a same value as a depth of the first drift region. The first drift region and the second drift region may be formed at the same time, using the gate electrode as a part of the implanting mask.

Abstract translation: 功率金属氧化物半导体场效应晶体管（MOSFET）及其形成方法。 功率MOSFET可以包括形成在栅极侧的第一漂移区域和与第一漂移区域相邻的栅电极下方的第二漂移区域，其深度小于第一漂移区域的深度，使得 第一漂移区域和第二漂移区域一起形成阶梯形状。 第二漂移区域的深度，栅极电介质的深度和栅电极的深度之和可以与第一漂移区域的深度基本相同。 可以使用栅电极作为植入掩模的一部分，同时形成第一漂移区域和第二漂移区域。

公开(公告)号：US20170186865A1

公开(公告)日：2017-06-29

申请号：US15458793

申请日：2017-03-14

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Fu-Yu Chu ,  Chih-Chang Cheng ,  Tung-Yang Lin ,  Ruey-Hsin Liu

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/40 ,  H01L29/08 ,  H01L29/10

CPC classification number: H01L29/7823 ,  H01L21/26513 ,  H01L21/26586 ,  H01L21/266 ,  H01L29/0847 ,  H01L29/0865 ,  H01L29/0878 ,  H01L29/0882 ,  H01L29/1045 ,  H01L29/1095 ,  H01L29/402 ,  H01L29/66659 ,  H01L29/66681 ,  H01L29/7816 ,  H01L29/7835

Abstract: Power Metal-Oxide-Semiconductor Field-Effect Transistors (MOSFETs) and methods of forming the same are provided. A power MOSFET may comprise a first drift region formed at a side of a gate electrode, and a second drift region beneath the gate electrode, adjacent to the first drift region, with a depth less than a depth of the first drift region so that the first drift region and the second drift region together form a stepwise shape. A sum of a depth of the second drift region, a depth of the gate dielectric, and a depth of the gate electrode may be of substantially a same value as a depth of the first drift region. The first drift region and the second drift region may be formed at the same time, using the gate electrode as a part of the implanting mask.

公开(公告)号：US09431531B2

公开(公告)日：2016-08-30

申请号：US14089803

申请日：2013-11-26

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Tung-Yang Lin ,  Hsin-Chih Chiang ,  Ruey-Hsin Liu ,  Ming-Ta Lei

IPC: H01L29/78 ,  H01L21/74 ,  H01L29/786 ,  H01L29/10

CPC classification number: H01L29/7824 ,  H01L21/743 ,  H01L29/1087 ,  H01L29/78624

Abstract: A semiconductor device configured to provide high heat dissipation and improve breakdown voltage comprises a substrate, a buried oxide layer over the substrate, a buried n+ region in the substrate below the buried oxide layer, and an epitaxial layer over the buried oxide layer. The epitaxial layer comprises a p-well, an n-well, and a drift region between the p-well and the n-well. The semiconductor device also comprises a source contact, a first electrode electrically connecting the source contact to the p-well, and a gate over a portion of the p-well and a portion of the drift region. The semiconductor device further comprises a drain contact, and a second electrode extending from the drain contact through the n-well and through the buried oxide layer to the buried n+ region. The second electrode electrically connects the drain contact to the n-well and to the buried n+ region.

Abstract translation: 配置为提供高散热并改善击穿电压的半导体器件包括衬底，衬底上的掩埋氧化物层，掩埋氧化物层下面的衬底中的掩埋的n +区，以及在掩埋氧化物层上的外延层。 外延层包括p阱，n阱以及p阱和n阱之间的漂移区。 半导体器件还包括源极接触，将源极接触电连接到p阱的第一电极以及p阱的一部分和漂移区的一部分上的栅极。 半导体器件还包括漏极接触，以及从漏极接触通过n阱延伸并穿过掩埋氧化物层到掩埋的n +区域的第二电极。 第二电极将漏极接触电连接到n阱和掩埋的n +区域。

公开(公告)号：US20160247914A1

公开(公告)日：2016-08-25

申请号：US15147569

申请日：2016-05-05

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Fu-Yu Chu ,  Chih-Chang Cheng ,  Tung-Yang Lin ,  Ruey-Hsin Liu

IPC: H01L29/78 ,  H01L29/10 ,  H01L29/66 ,  H01L29/40 ,  H01L21/266 ,  H01L21/265 ,  H01L29/08

CPC classification number: H01L29/7823 ,  H01L21/26513 ,  H01L21/26586 ,  H01L21/266 ,  H01L29/0847 ,  H01L29/0865 ,  H01L29/0878 ,  H01L29/0882 ,  H01L29/1045 ,  H01L29/1095 ,  H01L29/402 ,  H01L29/66659 ,  H01L29/66681 ,  H01L29/7816 ,  H01L29/7835

Abstract: Power Metal-Oxide-Semiconductor Field-Effect Transistors (MOSFETs) and methods of forming the same are provided. A power MOSFET may comprise a first drift region formed at a side of a gate electrode, and a second drift region beneath the gate electrode, adjacent to the first drift region, with a depth less than a depth of the first drift region so that the first drift region and the second drift region together form a stepwise shape. A sum of a depth of the second drift region, a depth of the gate dielectric, and a depth of the gate electrode may be of substantially a same value as a depth of the first drift region. The first drift region and the second drift region may be formed at the same time, using the gate electrode as a part of the implanting mask.

公开(公告)号：US20240321894A1

公开(公告)日：2024-09-26

申请号：US18668333

申请日：2024-05-20

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Hsin-Chih Chiang ,  Tung-Yang Lin ,  Ruey-Hsin Liu ,  Ming-Ta Lei

IPC: H01L27/12 ,  H01L21/74 ,  H01L21/762 ,  H01L21/768 ,  H01L21/84 ,  H01L23/48 ,  H01L29/06 ,  H01L29/10 ,  H01L29/423

CPC classification number: H01L27/1203 ,  H01L21/743 ,  H01L21/76283 ,  H01L21/76898 ,  H01L21/84 ,  H01L23/481 ,  H01L29/0653 ,  H01L29/1083 ,  H01L29/1087 ,  H01L29/4238

Abstract: Various embodiments of the present disclosure are directed towards an integrated chip. The integrated chip includes a first well region, a second well region, and a third well region disposed within a semiconductor substrate. The second well region is disposed between the first and second well regions. A first source/drain region is in the first well region. A second source/drain region is in the second well region. A gate structure is on the semiconductor substrate and spaced laterally between the first and second source/drain regions. A contact region is disposed in the third well region. A conductive structure is on the semiconductor substrate and spaced laterally between the second source/drain region and the contact region.

公开(公告)号：US11532701B2

公开(公告)日：2022-12-20

申请号：US17199152

申请日：2021-03-11

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Hsin-Fu Lin ,  Tsung-Hao Yeh ,  Chien-Hung Liu ,  Shiang-Hung Huang ,  Chih-Wei Hung ,  Tung-Yang Lin ,  Ruey-Hsin Liu ,  Chih-Chang Cheng

IPC: H01L29/06 ,  H01L21/762 ,  H01L29/10 ,  H01L27/12 ,  H01L29/41 ,  H01L29/40

Abstract: A semiconductor isolation structure includes a handle layer, a buried insulation layer, a semiconductor layer, a deep trench isolation structure, and a heavy doping region. The buried insulation layer is disposed on the handle layer. The semiconductor layer is disposed on the buried insulation layer and has a doping type. The semiconductor layer has a functional area in which doped regions of a semiconductor device are to be formed. The deep trench isolation structure penetrates the semiconductor layer and the buried insulation layer, and surrounds the functional area. The heavy doping region is formed in the semiconductor layer, is disposed between the functional area and the deep trench isolation structure, and is surrounded by the deep trench isolation structure. The heavy doping region has the doping type. A doping concentration of the heavy doping region is higher than that of the semiconductor layer.

公开(公告)号：US10014288B2

公开(公告)日：2018-07-03

申请号：US15173835

申请日：2016-06-06

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Hsin-Chih Chiang ,  Tung-Yang Lin ,  Ruey-Hsin Liu ,  Ming-Ta Lei

IPC: H01L27/02 ,  H01L29/66 ,  H01L29/861 ,  H01L29/06

CPC classification number: H01L27/0255 ,  H01L29/0619 ,  H01L29/0623 ,  H01L29/063 ,  H01L29/66121 ,  H01L29/861

Abstract: A semiconductor device includes a semiconductor substrate. A first semiconductor region is over a portion of the semiconductor substrate to a first depth. A second semiconductor region is in the first semiconductor region. A third semiconductor region is in the first semiconductor region. A fourth semiconductor region is outside the first semiconductor region. A fifth semiconductor region is outside the first semiconductor region to a fifth depth, the fifth semiconductor region being adjacent the fourth semiconductor region. A sixth semiconductor region is below the fifth semiconductor region and to a sixth depth. The sixth depth is equal to the first depth. A first electrode is connected to the third semiconductor region. A second electrode is connected to the fourth and fifth semiconductor regions. The fifth semiconductor region is configured to cause an increase in a current during a cathode to anode positive bias operation between the first and second electrodes.