公开(公告)号：US11923429B2

公开(公告)日：2024-03-05

申请号：US17405307

申请日：2021-08-18

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Chih-Chang Cheng ,  Fu-Yu Chu ,  Ming-Ta Lei ,  Ruey-Hsin Liu ,  Shih-Fen Huang

IPC分类号： H01L29/423 ,  H01L21/265 ,  H01L21/28 ,  H01L29/06 ,  H01L29/08 ,  H01L29/78 ,  H01L29/49

CPC分类号： H01L29/4238 ,  H01L21/26513 ,  H01L21/28123 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/78 ,  H01L29/4916

摘要： A semiconductor device and method for forming the semiconductor device are provided. In some embodiments, a semiconductor substrate comprises a device region. An isolation structure extends laterally in a closed path to demarcate the device region. A first source/drain region and a second source/drain region are in the device region and laterally spaced. A sidewall of the first source/drain region directly contacts the isolation structure at a first isolation structure sidewall, and remaining sidewalls of the first source/drain region are spaced from the isolation structure. A selectively-conductive channel is in the device region, and extends laterally from the first source/drain region to the second source/drain region. A plate comprises a central portion and a first peripheral portion. The central portion overlies the selectively-conductive channel, and the first peripheral portion protrudes from the central portion towards the first isolation structure sidewall.

公开(公告)号：US11817396B2

公开(公告)日：2023-11-14

申请号：US17388437

申请日：2021-07-29

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Chih-Chang Cheng ,  Fu-Yu Chu ,  Ruey-Hsin Liu

IPC分类号： H01L21/762 ,  H01L29/78 ,  H01L23/552 ,  H01L29/66 ,  H01L21/285

CPC分类号： H01L23/552 ,  H01L21/28518 ,  H01L21/762 ,  H01L29/66477 ,  H01L29/78

摘要： In some embodiments, a semiconductor device is provided. The semiconductor device includes an isolation structure disposed in a semiconductor substrate, where an inner perimeter of the isolation structure demarcates a device region of the semiconductor substrate. A gate is disposed over the device region, where an outer perimeter of the gate is disposed within the inner perimeter of the isolation structure. A first source/drain region is disposed in the device region and on a first side of the gate. A second source/drain region is disposed in the device region and on a second side of the gate opposite the first side. A silicide blocking structure partially covers the gate, partially covers the first source/drain region, and partially covers the isolation structure, where a first sidewall of the silicide blocking structure is disposed between first opposite sidewalls of the gate.

公开(公告)号：US20210376100A1

公开(公告)日：2021-12-02

申请号：US17405307

申请日：2021-08-18

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Chih-Chang Cheng ,  Fu-Yu Chu ,  Ming-Ta Lei ,  Ruey-Hsin Liu ,  Shih-Fen Huang

IPC分类号： H01L29/423 ,  H01L29/78 ,  H01L21/265 ,  H01L21/28 ,  H01L29/06 ,  H01L29/08

摘要： A semiconductor device and method for forming the semiconductor device are provided. In some embodiments, a semiconductor substrate comprises a device region. An isolation structure extends laterally in a closed path to demarcate the device region. A first source/drain region and a second source/drain region are in the device region and laterally spaced. A sidewall of the first source/drain region directly contacts the isolation structure at a first isolation structure sidewall, and remaining sidewalls of the first source/drain region are spaced from the isolation structure. A selectively-conductive channel is in the device region, and extends laterally from the first source/drain region to the second source/drain region. A plate comprises a central portion and a first peripheral portion. The central portion overlies the selectively-conductive channel, and the first peripheral portion protrudes from the central portion towards the first isolation structure sidewall.

公开(公告)号：US10205024B2

公开(公告)日：2019-02-12

申请号：US15017225

申请日：2016-02-05

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

发明人： Chih-Chang Cheng ,  Fu-Yu Chu ,  Ruey-Hsin Liu ,  Kuang-Hsin Chen ,  Chih-Hsin Ko ,  Shih-Fen Huang

IPC分类号： H01L29/78 ,  H01L29/66 ,  H01L29/06 ,  H01L29/40 ,  H01L29/417

摘要： A semiconductor structure is disclosed. The semiconductor structure includes: a substrate; a gate structure formed over the substrate; a source region and a drain region formed in the substrate on either side of the gate structure, the source region and the drain region both having a first type of conductivity; and a field plate formed over the substrate between the gate structure and the drain region; wherein the field plate is coupled to the source region or a bulk electrode of the substrate. An associated method for fabricating the semiconductor structure is also disclosed.

公开(公告)号：US09917212B1

公开(公告)日：2018-03-13

申请号：US15257291

申请日：2016-09-06

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

发明人： Fu-Yu Chu ,  Chih-Chang Cheng ,  Ruey-Hsin Liu

IPC分类号： H01L29/808 ,  H01L29/08 ,  H01L29/06 ,  H01L27/146 ,  H01L29/45 ,  H01L29/423 ,  H01L29/66

CPC分类号： H01L29/808 ,  H01L27/14614 ,  H01L27/14616 ,  H01L27/14643 ,  H01L29/0653 ,  H01L29/402 ,  H01L29/66901 ,  H01L29/7832

摘要： The present disclosure provides a transistor structure, including a self-aligned source-drain structure surrounded by an insulating structure and a gate of a second conductive type separated from the source and the drain by the insulating structure. The self-aligned source-drain structure includes a source and a drain of a first conductive type, a channel between the source and the drain, and a polysilicon contact over and aligned with the channel. A method for manufacturing the transistor structure is also provided in the present disclosure.

公开(公告)号：US12074208B2

公开(公告)日：2024-08-27

申请号：US16700933

申请日：2019-12-02

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

发明人： Chih-Chang Cheng ,  Fu-Yu Chu ,  Ruey-Hsin Liu

IPC分类号： H01L29/66 ,  H01L21/768 ,  H01L23/535 ,  H01L29/06 ,  H01L29/735 ,  H01L29/861 ,  H02M3/156

CPC分类号： H01L29/6625 ,  H01L21/76895 ,  H01L23/535 ,  H01L29/0607 ,  H01L29/0653 ,  H01L29/66136 ,  H01L29/735 ,  H01L29/861 ,  H02M3/156

摘要： A method of making a triple well isolated diode includes forming a buried layer in a substrate. The method further includes forming an epi-layer over the substrate and the buried layer. The method further includes forming a first well in the epi-layer, wherein the first well forms an interface with the buried layer. The method further includes forming a second well in the epi-layer surrounding the first well. The method further includes forming a third well in the epi-layer surrounding the second well. The method further includes forming a deep well in the epi-layer beneath the first well to electrically connect to the second well. The method further includes forming a first plurality of isolation features between the first well and the second well. The method further includes forming a second plurality of isolation features between the third well and the epi-layer.

公开(公告)号：US11769812B2

公开(公告)日：2023-09-26

申请号：US17203323

申请日：2021-03-16

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

发明人： Chih-Chang Cheng ,  Fu-Yu Chu ,  Ruey-Hsin Liu

IPC分类号： H01L29/423 ,  H01L29/78 ,  H01L29/66 ,  H01L29/94 ,  H01L27/06 ,  H01L21/8238 ,  H01L27/092

CPC分类号： H01L29/42368 ,  H01L29/6659 ,  H01L29/66659 ,  H01L29/7833 ,  H01L29/7835 ,  H01L29/94 ,  H01L21/823857 ,  H01L27/06 ,  H01L27/0617 ,  H01L27/092 ,  H01L27/0928 ,  H01L29/66492

摘要： A semiconductor device includes a substrate and a gate structure over the substrate. The semiconductor device includes a source in the substrate on a first side of the gate structure. The semiconductor device further includes a drain in the substrate on a second side of the gate structure. The semiconductor device further includes a first well having a first dopant type, wherein the first well contacts at least two surfaces of the source. The semiconductor device further includes a second well having the first dopant type, wherein the second well contacts at least two surfaces of the drain. The semiconductor device further includes a deep well below the first well and below the second well, wherein the second well extends between the first well and the deep well. In some embodiments, the deep well has a second dopant type, and the second dopant type is opposite the first dopant type.

公开(公告)号：US10038090B2

公开(公告)日：2018-07-31

申请号：US15458793

申请日：2017-03-14

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Fu-Yu Chu ,  Chih-Chang Cheng ,  Tung-Yang Lin ,  Ruey-Hsin Liu

IPC分类号： H01L29/78 ,  H01L27/092 ,  H01L29/08 ,  H01L29/10 ,  H01L29/40 ,  H01L29/66

CPC分类号： H01L29/7823 ,  H01L21/26513 ,  H01L21/26586 ,  H01L21/266 ,  H01L29/0847 ,  H01L29/0865 ,  H01L29/0878 ,  H01L29/0882 ,  H01L29/1045 ,  H01L29/1095 ,  H01L29/402 ,  H01L29/66659 ,  H01L29/66681 ,  H01L29/7816 ,  H01L29/7835

摘要： Power Metal-Oxide-Semiconductor Field-Effect Transistors (MOSFETs) and methods of forming the same are provided. A power MOSFET may comprise a first drift region formed at a side of a gate electrode, and a second drift region beneath the gate electrode, adjacent to the first drift region, with a depth less than a depth of the first drift region so that the first drift region and the second drift region together form a stepwise shape. A sum of a depth of the second drift region, a depth of the gate dielectric, and a depth of the gate electrode may be of substantially a same value as a depth of the first drift region. The first drift region and the second drift region may be formed at the same time, using the gate electrode as a part of the implanting mask.

公开(公告)号：US09601616B2

公开(公告)日：2017-03-21

申请号：US15147569

申请日：2016-05-05

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Fu-Yu Chu ,  Chih-Chang Cheng ,  Tung-Yang Lin ,  Ruey-Hsin Liu

IPC分类号： H01L21/336 ,  H01L29/78 ,  H01L21/266 ,  H01L29/08 ,  H01L29/10 ,  H01L29/40 ,  H01L29/66 ,  H01L21/265

CPC分类号： H01L29/7823 ,  H01L21/26513 ,  H01L21/26586 ,  H01L21/266 ,  H01L29/0847 ,  H01L29/0865 ,  H01L29/0878 ,  H01L29/0882 ,  H01L29/1045 ,  H01L29/1095 ,  H01L29/402 ,  H01L29/66659 ,  H01L29/66681 ,  H01L29/7816 ,  H01L29/7835

摘要： Power Metal-Oxide-Semiconductor Field-Effect Transistors (MOSFETs) and methods of forming the same are provided. A power MOSFET may comprise a first drift region formed at a side of a gate electrode, and a second drift region beneath the gate electrode, adjacent to the first drift region, with a depth less than a depth of the first drift region so that the first drift region and the second drift region together form a stepwise shape. A sum of a depth of the second drift region, a depth of the gate dielectric, and a depth of the gate electrode may be of substantially a same value as a depth of the first drift region. The first drift region and the second drift region may be formed at the same time, using the gate electrode as a part of the implanting mask.

公开(公告)号：US09583618B2

公开(公告)日：2017-02-28

申请号：US13928971

申请日：2013-06-27

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

发明人： Chih-Chang Cheng ,  Fu-Yu Chu ,  Ruey-Hsin Liu

IPC分类号： H01L29/78 ,  H01L29/66 ,  H01L27/06 ,  H01L21/8234 ,  H01L21/265 ,  H01L29/10

CPC分类号： H01L29/7835 ,  H01L21/26513 ,  H01L21/823418 ,  H01L29/1045 ,  H01L29/66492 ,  H01L29/66659

摘要： A metal-oxide-semiconductor field effect transistor (MOSFET) includes a substrate and a gate structure over a top surface of the substrate. The MOSFET further includes a source in the substrate on a first side of the gate structure and a drain in the substrate on a second side of the gate structure opposite the first side. A surface portion of the substrate extending from the source to the drain has an asymmetric dopant concentration profile.

摘要翻译： 金属氧化物半导体场效应晶体管（MOSFET）包括衬底和在衬底顶表面上的栅极结构。 MOSFET还包括在栅极结构的第一侧上的衬底中的源极和在栅极结构的与第一侧相对的第二侧的衬底中的漏极。 从源极到漏极延伸的衬底的表面部分具有不对称的掺杂剂浓度分布。