公开(公告)号：US09269585B2

公开(公告)日：2016-02-23

申请号：US14152497

申请日：2014-01-10

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Shich-Chang Suen ,  Li-Chieh Wu ,  Chi-Jen Liu ,  He Hui Peng ,  Liang-Guang Chen ,  Yung-Chung Chen

IPC: H01L21/3205 ,  H01L21/4763 ,  H01L21/28 ,  H01L21/02 ,  H01L21/311

CPC classification number: H01L21/02068 ,  H01L21/02063 ,  H01L21/0234 ,  H01L21/28079 ,  H01L21/28132 ,  H01L21/288 ,  H01L21/31105 ,  H01L21/31111 ,  H01L21/31116 ,  H01L21/76804 ,  H01L21/76814 ,  H01L21/76831 ,  H01L21/76877 ,  H01L21/76895 ,  H01L29/401 ,  H01L29/66545

Abstract: The present disclosure provides a method for forming an integrated circuit (IC) structure. The method includes providing a metal gate (MG), an etch stop layer (ESL) formed on the MG, and a dielectric layer formed on the ESL. The method further includes etching the ESL and the dielectric layer to form a trench. A surface of the MG exposed in the trench is oxidized to form a first oxide layer on the MG. The method further includes removing the first oxide layer using a H3PO4 solution.

Abstract translation: 本公开提供了一种用于形成集成电路（IC）结构的方法。 该方法包括提供金属栅极（MG），形成在MG上的蚀刻停止层（ESL）以及形成在ESL上的电介质层。 该方法还包括蚀刻ESL和介电层以形成沟槽。 暴露在沟槽中的MG的表面被氧化以在MG上形成第一氧化物层。 该方法还包括使用H 3 PO 4溶液去除第一氧化物层。

公开(公告)号：US11410846B2

公开(公告)日：2022-08-09

申请号：US17094563

申请日：2020-11-10

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Shich-Chang Suen ,  Li-Chieh Wu ,  Chi-Jen Liu ,  He Hui Peng ,  Liang-Guang Chen ,  Yung-Chung Chen

IPC: H01L21/02 ,  H01L21/28 ,  H01L21/311 ,  H01L21/768 ,  H01L21/288 ,  H01L29/66

Abstract: The present disclosure provides a method for forming an integrated circuit (IC) structure. The method includes providing a metal gate (MG), an etch stop layer (ESL) formed on the MG, and a dielectric layer formed on the ESL. The method further includes etching the ESL and the dielectric layer to form a trench. A surface of the MG exposed in the trench is oxidized to form a first oxide layer on the MG. The method further includes removing the first oxide layer using a H3PO4 solution.

公开(公告)号：US20210082688A1

公开(公告)日：2021-03-18

申请号：US17094563

申请日：2020-11-10

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Shich-Chang Suen ,  Li-Chieh Wu ,  Chi-Jen Liu ,  He Hui Peng ,  Liang-Guang Chen ,  Yung-Chung Chen

IPC: H01L21/02 ,  H01L21/28 ,  H01L21/311 ,  H01L21/768 ,  H01L29/40 ,  H01L21/288

Abstract: The present disclosure provides a method for forming an integrated circuit (IC) structure. The method includes providing a metal gate (MG), an etch stop layer (ESL) formed on the MG, and a dielectric layer formed on the ESL. The method further includes etching the ESL and the dielectric layer to form a trench. A surface of the MG exposed in the trench is oxidized to form a first oxide layer on the MG. The method further includes removing the first oxide layer using a H3PO4 solution.

公开(公告)号：US20170221700A1

公开(公告)日：2017-08-03

申请号：US15492034

申请日：2017-04-20

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Shich-Chang Suen ,  Li-Chieh Wu ,  Chi-Jen Liu ,  He Hui Peng ,  Liang-Guang Chen ,  Yung-Chung Chen

IPC: H01L21/02 ,  H01L21/288 ,  H01L21/768 ,  H01L21/311

CPC classification number: H01L21/02068 ,  H01L21/02063 ,  H01L21/0234 ,  H01L21/28079 ,  H01L21/28132 ,  H01L21/288 ,  H01L21/31105 ,  H01L21/31111 ,  H01L21/31116 ,  H01L21/76804 ,  H01L21/76814 ,  H01L21/76831 ,  H01L21/76877 ,  H01L21/76895 ,  H01L29/401 ,  H01L29/66545

Abstract: The present disclosure provides a method for forming an integrated circuit (IC) structure. The method includes providing a metal gate (MG), an etch stop layer (ESL) formed on the MG, and a dielectric layer formed on the ESL. The method further includes etching the ESL and the dielectric layer to form a trench. A surface of the MG exposed in the trench is oxidized to form a first oxide layer on the MG. The method further includes removing the first oxide layer using a H3PO4 solution.

公开(公告)号：US09653594B2

公开(公告)日：2017-05-16

申请号：US15011873

申请日：2016-02-01

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Wen-Chi Tsai ,  Chia-Han Lai ,  Yung-Chung Chen ,  Mei-Yun Wang ,  Chii-Ming Wu ,  Fang-Cheng Chen ,  Huang-Ming Chen ,  Ming-Ta Lei

IPC: H01L21/768 ,  H01L29/78 ,  H01L21/285 ,  H01L29/417 ,  H01L21/02 ,  H01L23/535 ,  H01L29/45 ,  H01L29/66

CPC classification number: H01L29/78 ,  H01L21/02063 ,  H01L21/28512 ,  H01L21/28518 ,  H01L21/76802 ,  H01L21/76805 ,  H01L21/76814 ,  H01L21/76825 ,  H01L21/76831 ,  H01L21/76844 ,  H01L21/76855 ,  H01L23/485 ,  H01L23/535 ,  H01L29/41775 ,  H01L29/45 ,  H01L29/6659 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A system and method for forming and using a liner is provided. An embodiment comprises forming an opening in an inter-layer dielectric over a substrate and forming the liner along the sidewalls of the opening. A portion of the liner is removed from a bottom of the opening, and a cleaning process may be performed through the liner. By using the liner, damage to the sidewalls of the opening from the cleaning process may be reduced or eliminated. Additionally, the liner may be used to help implantation of ions within the substrate.

公开(公告)号：US20160163847A1

公开(公告)日：2016-06-09

申请号：US15011873

申请日：2016-02-01

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Wen-Chi Tsai ,  Chia-Han Lai ,  Yung-Chung Chen ,  Mei-Yun Wang ,  Chii-Ming Wu ,  Fang-Cheng Chen ,  Huang-Ming Chen ,  Ming-Ta Lei

IPC: H01L29/78 ,  H01L29/45 ,  H01L23/535

CPC classification number: H01L29/78 ,  H01L21/02063 ,  H01L21/28512 ,  H01L21/28518 ,  H01L21/76802 ,  H01L21/76805 ,  H01L21/76814 ,  H01L21/76825 ,  H01L21/76831 ,  H01L21/76844 ,  H01L21/76855 ,  H01L23/485 ,  H01L23/535 ,  H01L29/41775 ,  H01L29/45 ,  H01L29/6659 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A system and method for forming and using a liner is provided. An embodiment comprises forming an opening in an inter-layer dielectric over a substrate and forming the liner along the sidewalls of the opening. A portion of the liner is removed from a bottom of the opening, and a cleaning process may be performed through the liner. By using the liner, damage to the sidewalls of the opening from the cleaning process may be reduced or eliminated. Additionally, the liner may be used to help implantation of ions within the substrate.

公开(公告)号：US12119345B2

公开(公告)日：2024-10-15

申请号：US17395879

申请日：2021-08-06

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

Inventor： Chia-Ho Chu ,  Yung-Chung Chen ,  Chih-Tang Peng

IPC: H01L27/088 ,  H01L21/02 ,  H01L21/8234

CPC classification number: H01L27/0886 ,  H01L21/0234 ,  H01L21/823431 ,  H01L21/823481

Abstract: A semiconductor structure includes a first FinFET device disposed over a substrate, a second FinFET device disposed over the substrate, and an isolation structure. The first FinFET device includes at least a first fin and a first metal gate structure over the first fin. The second FinFET device includes at least a second fin and a second metal gate structure over the second fin. The isolation structure is disposed between the first metal gate structure and the second metal gate structure. The isolation structure includes a dielectric feature and a dielectric layer. The dielectric layer is between the dielectric feature and the first metal gate structure, between the dielectric feature and the second metal gate structure, and between the dielectric feature and the substrate. The dielectric feature and the dielectric layer include different materials and different thicknesses.

公开(公告)号：US11996283B2

公开(公告)日：2024-05-28

申请号：US17874152

申请日：2022-07-26

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Shich-Chang Suen ,  Li-Chieh Wu ,  Chi-Jen Liu ,  He Hui Peng ,  Liang-Guang Chen ,  Yung-Chung Chen

IPC: H01L21/28 ,  H01L21/02 ,  H01L21/288 ,  H01L21/311 ,  H01L21/768 ,  H01L29/66

CPC classification number: H01L21/02068 ,  H01L21/02063 ,  H01L21/0234 ,  H01L21/28079 ,  H01L21/28132 ,  H01L21/288 ,  H01L21/31105 ,  H01L21/31111 ,  H01L21/31116 ,  H01L21/76804 ,  H01L21/76814 ,  H01L21/76831 ,  H01L21/76877 ,  H01L21/76895 ,  H01L29/40114 ,  H01L29/66545

Abstract: The present disclosure provides a method for forming an integrated circuit (IC) structure. The method includes providing a metal gate (MG), an etch stop layer (ESL) formed on the MG, and a dielectric layer formed on the ESL. The method further includes etching the ESL and the dielectric layer to form a trench. A surface of the MG exposed in the trench is oxidized to form a first oxide layer on the MG. The method further includes removing the first oxide layer using a H3PO4 solution.

公开(公告)号：US20220359189A1

公开(公告)日：2022-11-10

申请号：US17874152

申请日：2022-07-26

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Shich-Chang Suen ,  Li-Chieh Wu ,  Chi-Jen Liu ,  He Hui Peng ,  Liang-Guang Chen ,  Yung-Chung Chen

IPC: H01L21/02 ,  H01L21/28 ,  H01L21/311 ,  H01L21/768 ,  H01L21/288

Abstract: The present disclosure provides a method for forming an integrated circuit (IC) structure. The method includes providing a metal gate (MG), an etch stop layer (ESL) formed on the MG, and a dielectric layer formed on the ESL. The method further includes etching the ESL and the dielectric layer to form a trench. A surface of the MG exposed in the trench is oxidized to form a first oxide layer on the MG. The method further includes removing the first oxide layer using a H3PO4 solution.

公开(公告)号：US09633832B2

公开(公告)日：2017-04-25

申请号：US15049420

申请日：2016-02-22

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Shich-Chang Suen ,  Li-Chieh Wu ,  Chi-Jen Liu ,  He Hui Peng ,  Liang-Guang Chen ,  Yung-Chung Chen

IPC: H01L21/3205 ,  H01L21/4763 ,  H01L21/02 ,  H01L21/28 ,  H01L21/311 ,  H01L21/768 ,  H01L29/40 ,  H01L29/66

CPC classification number: H01L21/02068 ,  H01L21/02063 ,  H01L21/0234 ,  H01L21/28079 ,  H01L21/28132 ,  H01L21/288 ,  H01L21/31105 ,  H01L21/31111 ,  H01L21/31116 ,  H01L21/76804 ,  H01L21/76814 ,  H01L21/76831 ,  H01L21/76877 ,  H01L21/76895 ,  H01L29/401 ,  H01L29/66545

Abstract: The present disclosure provides a method for forming an integrated circuit (IC) structure. The method includes providing a metal gate (MG), an etch stop layer (ESL) formed on the MG, and a dielectric layer formed on the ESL. The method further includes etching the ESL and the dielectric layer to form a trench. A surface of the MG exposed in the trench is oxidized to form a first oxide layer on the MG. The method further includes removing the first oxide layer using a H3PO4 solution.