公开(公告)号：US10515945B2

公开(公告)日：2019-12-24

申请号：US16214177

申请日：2018-12-10

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Chih Wei Lu ,  Chung-Ju Lee ,  Chien-Hua Huang ,  Hsiang-Ku Shen ,  Zhao-Cheng Chen

IPC分类号： H01L23/528 ,  H01L21/768 ,  H01L27/02 ,  H01L27/088 ,  H01L21/3105 ,  H01L21/8234 ,  H01L29/66 ,  H01L21/467 ,  H01L23/522 ,  H01L29/06 ,  H01L23/485

摘要： A semiconductor device includes a first conductive structure directly over an isolation structure; a second conductive structure directly over an active region; a first dielectric layer over the first and second conductive structures; a second dielectric layer over the first dielectric layer, wherein the first and second dielectric layers include different materials; a first conductive feature contacting the first conductive structure through at least the first and second dielectric layers; and a second conductive feature contacting the second conductive structure through at least the first and second dielectric layers, wherein the first and second conductive features include a same metal.

公开(公告)号：US10418456B2

公开(公告)日：2019-09-17

申请号：US15614274

申请日：2017-06-05

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Yu-Lien Huang ,  Chi-Wen Liu ,  Clement Hsingjen Wann ,  Ming-Huan Tsai ,  Zhao-Cheng Chen

IPC分类号： H01L21/02 ,  H01L29/49 ,  H01L29/51 ,  H01L29/66 ,  H01L29/78 ,  H01L29/423

摘要： A method of forming a semiconductor device having a semiconductor substrate with a dielectric layer disposed thereon. A trench is defined in the dielectric layer. A metal gate structure is formed in the trench. The metal gate structure includes a first layer and a second layer disposed on the first layer. The first layer extends to a first height in the trench and the second layer extends to a second height in the trench; the second height is greater than the first height. In some embodiments, the second layer is a work function metal and the first layer is a dielectric. In some embodiments, the second layer is a barrier layer.

公开(公告)号：US09947646B2

公开(公告)日：2018-04-17

申请号：US15493847

申请日：2017-04-21

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Chih Wei Lu ,  Chung-Ju Lee ,  Chien-Hua Huang ,  Hsiang-Ku Shen ,  Zhao-Cheng Chen

IPC分类号： H01L21/8234 ,  H01L27/02 ,  H01L29/06 ,  H01L23/522 ,  H01L21/768 ,  H01L27/088 ,  H01L23/528 ,  H01L29/66

CPC分类号： H01L27/0207 ,  H01L21/31055 ,  H01L21/467 ,  H01L21/76816 ,  H01L21/7684 ,  H01L21/76877 ,  H01L21/823475 ,  H01L23/5226 ,  H01L23/528 ,  H01L27/088 ,  H01L29/0649 ,  H01L29/665 ,  H01L29/66515 ,  H01L29/66545

摘要： A semiconductor device includes a substrate having first and second regions. The first region includes an insulator and the second region includes source, drain, and channel regions of a transistor. The semiconductor device further includes first and second gate stacks over the insulator; a third gate stack over the channel region; a first dielectric layer over the first, second, and third gate stacks; a second dielectric layer over the first dielectric layer; and a metal layer over the first and second gate stacks. The metal layer is in electrical communication with the second gate stack and is isolated from the first gate stack by at least the first and second dielectric layers.

公开(公告)号：US09202691B2

公开(公告)日：2015-12-01

申请号：US13745205

申请日：2013-01-18

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

发明人： Yu-Lien Huang ,  Chi-Wen Liu ,  Zhao-Cheng Chen ,  Ming-Huan Tsai ,  Clement Hsingjen Wann

IPC分类号： H01L29/78 ,  H01L21/02 ,  H01L29/49 ,  H01L29/66 ,  H01L29/51

CPC分类号： H01L29/4966 ,  H01L21/02697 ,  H01L29/42368 ,  H01L29/42376 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/78 ,  H01L29/7833

摘要： In one embodiment, a method includes providing a semiconductor substrate having a trench disposed thereon and forming a plurality of layers in the trench. The plurality of layers formed in the trench is etched thereby providing at least one etched layer having a top surface that lies below a top surface of the trench. In a further embodiment, this may provide for a substantially v-shaped opening or entry to the trench for the formation of further layers.

摘要翻译： 在一个实施例中，一种方法包括提供其上设置有沟槽并在沟槽中形成多个层的半导体衬底。 蚀刻形成在沟槽中的多个层，从而提供至少一个具有位于沟槽顶表面下方的顶表面的蚀刻层。 在另一个实施例中，这可以提供用于形成另外的层的大致v形的开口或沟槽的入口。

公开(公告)号：US10971594B2

公开(公告)日：2021-04-06

申请号：US16572438

申请日：2019-09-16

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Yu-Lien Huang ,  Chi-Wen Liu ,  Clement Hsingjen Wann ,  Ming-Huan Tsai ,  Zhao-Cheng Chen

IPC分类号： H01L29/49 ,  H01L29/66 ,  H01L21/02 ,  H01L29/78 ,  H01L29/423 ,  H01L29/51

摘要： A semiconductor device has a semiconductor substrate with a dielectric layer disposed thereon. A trench is defined in the dielectric layer. A metal gate structure is disposed in the trench. The metal gate structure includes a first layer and a second layer disposed on the first layer. The first layer extends to a first height in the trench and the second layer extends to a second height in the trench; the second height is less than the first height.

公开(公告)号：US20190115336A1

公开(公告)日：2019-04-18

申请号：US16214177

申请日：2018-12-10

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Chih Wei Lu ,  Chung-Ju Lee ,  Chien-Hua Huang ,  Hsiang-Ku Shen ,  Zhao-Cheng Chen

IPC分类号： H01L27/02 ,  H01L21/8234 ,  H01L27/088 ,  H01L23/528 ,  H01L21/3105 ,  H01L21/768 ,  H01L29/66 ,  H01L29/06 ,  H01L23/522 ,  H01L21/467

摘要： A semiconductor device includes a first conductive structure directly over an isolation structure; a second conductive structure directly over an active region; a first dielectric layer over the first and second conductive structures; a second dielectric layer over the first dielectric layer, wherein the first and second dielectric layers include different materials; a first conductive feature contacting the first conductive structure through at least the first and second dielectric layers; and a second conductive feature contacting the second conductive structure through at least the first and second dielectric layers, wherein the first and second conductive features include a same metal.

公开(公告)号：US20170141104A1

公开(公告)日：2017-05-18

申请号：US14942678

申请日：2015-11-16

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Chih Wei Lu ,  Chung-Ju Lee ,  Chien-Hua Huang ,  Hsiang-Ku Shen ,  Zhao-Cheng Chen

IPC分类号： H01L27/088 ,  H01L23/528 ,  H01L21/8234 ,  H01L27/02 ,  H01L21/768 ,  H01L21/3105

CPC分类号： H01L27/0207 ,  H01L21/31055 ,  H01L21/467 ,  H01L21/76816 ,  H01L21/7684 ,  H01L21/76877 ,  H01L21/823475 ,  H01L23/5226 ,  H01L23/528 ,  H01L27/088 ,  H01L29/0649 ,  H01L29/665 ,  H01L29/66515 ,  H01L29/66545

摘要： A method of forming a semiconductor device provides a precursor that includes a substrate having first and second regions, wherein the first region includes an insulator and the second region includes source, drain, and channel regions of a transistor. The precursor further includes gate stacks over the insulator, and gate stacks over the channel regions. The precursor further includes a first dielectric layer over the gate stacks. The method further includes partially recessing the first dielectric layer; forming a second dielectric layer over the recessed first dielectric layer; and forming a contact etch stop (CES) layer over the second dielectric layer. In an embodiment, the method further includes forming gate via holes over the gate stacks, forming source and drain (S/D) via holes over the S/D regions, and forming vias in the gate via holes and S/D via holes.

公开(公告)号：US10163887B2

公开(公告)日：2018-12-25

申请号：US15952316

申请日：2018-04-13

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Chih Wei Lu ,  Chung-Ju Lee ,  Chien-Hua Huang ,  Hsiang-Ku Shen ,  Zhao-Cheng Chen

IPC分类号： H01L21/8234 ,  H01L27/02 ,  H01L27/088 ,  H01L21/768 ,  H01L21/3105 ,  H01L23/528 ,  H01L29/66 ,  H01L21/467 ,  H01L23/522 ,  H01L29/06

摘要： A semiconductor device includes a first gate stack over an insulator, a second gate stack over an active region, a first dielectric layer over the first and second gate stacks, a second dielectric layer over the first dielectric layer, and a metal layer over the first and second gate stacks. The first and second dielectric layers include different materials. The metal layer contacts the second gate stack by penetrating at least the first and second dielectric layers and is isolated from the first gate stack by at least the first and second dielectric layers.

公开(公告)号：US20160079383A1

公开(公告)日：2016-03-17

申请号：US14952733

申请日：2015-11-25

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Yu-Lien Huang ,  Chi-Wen Liu ,  Clement Hsingjen Wann ,  Ming-Huan Tsai ,  Zhao-Cheng Chen

IPC分类号： H01L29/49 ,  H01L29/423

CPC分类号： H01L29/4966 ,  H01L21/02697 ,  H01L29/42368 ,  H01L29/42376 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/78 ,  H01L29/7833

摘要： A semiconductor device having a semiconductor substrate with a dielectric layer disposed thereon. A trench is defined in the dielectric layer. A metal gate structure is disposed in the trench. The metal gate structure includes a first layer and a second layer disposed on the first layer. The first layer extends to a first height in the trench and the second layer extends to a second height in the trench; the second height is greater than the first height. In some embodiments, the second layer is a work function metal and the first layer is a dielectric. In some embodiments, the second layer is a barrier layer.

摘要翻译： 一种具有设置在其上的介电层的半导体衬底的半导体器件。 在电介质层中限定沟槽。 金属栅极结构设置在沟槽中。 金属栅极结构包括设置在第一层上的第一层和第二层。 第一层延伸到沟槽中的第一高度，第二层延伸到沟槽中的第二高度; 第二高度大于第一高度。 在一些实施例中，第二层是功函数金属，第一层是电介质。 在一些实施例中，第二层是阻挡层。

公开(公告)号：US20160043224A1

公开(公告)日：2016-02-11

申请号：US14918134

申请日：2015-10-20

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Yu-Lien Huang ,  Zhao-Cheng Chen

IPC分类号： H01L29/78 ,  H01L29/06 ,  H01L29/423 ,  H01L29/08 ,  H01L29/161 ,  H01L27/12 ,  H01L29/04

CPC分类号： H01L29/7848 ,  H01L21/02532 ,  H01L21/02579 ,  H01L21/0262 ,  H01L21/823412 ,  H01L21/823425 ,  H01L27/1207 ,  H01L29/045 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/161 ,  H01L29/165 ,  H01L29/42364 ,  H01L29/4966 ,  H01L29/66636

摘要： A semiconductor device and a method for fabricating the semiconductor device are disclosed. A gate stack is formed over a surface of the substrate. A recess cavity is formed in the substrate adjacent to the gate stack. A first epitaxial (epi) material is then formed in the recess cavity. A second epi material is formed over the first epi material. A portion of the second epi material is removed by a removing process. The disclosed method provides an improved method by providing a second epi material and the removing process for forming the strained feature, therefor, to enhance carrier mobility and upgrade the device performance.

摘要翻译： 公开了一种用于制造半导体器件的半导体器件和方法。 栅极叠层形成在衬底的表面上。 在与衬底相邻的衬底中形成凹槽。 然后在凹腔中形成第一外延（epi）材料。 在第一外延材料上形成第二外延材料。 通过去除过程去除第二外延材料的一部分。 所公开的方法通过提供第二外延材料和用于形成应变特征的去除过程来提供改进的方法，以增强载体移动性并提高装置性能。