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公开(公告)号：US09543301B2
公开(公告)日：2017-01-10
申请号：US14844809
申请日：2015-09-03
IPC分类号： H01L21/8238 , H01L29/10 , H01L27/092 , H01L29/66 , H01L29/16 , H01L29/165 , H01L29/78 , H01L29/06
CPC分类号： H01L27/0924 , H01L21/823807 , H01L21/823814 , H01L21/823821 , H01L21/823828 , H01L21/823864 , H01L21/823878 , H01L27/0922 , H01L29/0653 , H01L29/1054 , H01L29/16 , H01L29/165 , H01L29/66477 , H01L29/66545 , H01L29/66795 , H01L29/7848 , H01L29/785
摘要： Embodiments of the present disclosure are a FinFET device, and methods of forming a FinFET device. An embodiment is a method for forming a FinFET device, the method comprising forming a semiconductor strip over a semiconductor substrate, wherein the semiconductor strip is disposed in a dielectric layer, forming a gate over the semiconductor strip and the dielectric layer, and forming a first recess and a second recess in the semiconductor strip, wherein the first recess is on an opposite side of the gate from the second recess. The method further comprises forming a source region in the first recess and a drain region in the second recess, and recessing the dielectric layer, wherein a first portion of the semiconductor strip extends above a top surface of the dielectric layer forming a semiconductor fin.
摘要翻译： 本公开的实施例是FinFET器件，以及形成FinFET器件的方法。 一个实施例是一种用于形成FinFET器件的方法，该方法包括在半导体衬底上形成半导体条，其中半导体条布置在电介质层中，在半导体条和电介质层上形成栅极，并形成第一 凹部和半导体条中的第二凹部，其中第一凹部位于与第二凹部的栅极相反的一侧。 所述方法还包括在所述第一凹槽中形成源极区域和在所述第二凹槽中形成漏极区域，以及使所述电介质层凹陷，其中所述半导体薄膜的第一部分在形成半导体鳍片的介电层的顶表面上方延伸。
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公开(公告)号：US20160079383A1
公开(公告)日：2016-03-17
申请号：US14952733
申请日：2015-11-25
IPC分类号： H01L29/49 , H01L29/423
CPC分类号： H01L29/4966 , H01L21/02697 , H01L29/42368 , H01L29/42376 , H01L29/517 , H01L29/66545 , H01L29/78 , H01L29/7833
摘要： A semiconductor device having a semiconductor substrate with a dielectric layer disposed thereon. A trench is defined in the dielectric layer. A metal gate structure is disposed in the trench. The metal gate structure includes a first layer and a second layer disposed on the first layer. The first layer extends to a first height in the trench and the second layer extends to a second height in the trench; the second height is greater than the first height. In some embodiments, the second layer is a work function metal and the first layer is a dielectric. In some embodiments, the second layer is a barrier layer.
摘要翻译： 一种具有设置在其上的介电层的半导体衬底的半导体器件。 在电介质层中限定沟槽。 金属栅极结构设置在沟槽中。 金属栅极结构包括设置在第一层上的第一层和第二层。 第一层延伸到沟槽中的第一高度，第二层延伸到沟槽中的第二高度; 第二高度大于第一高度。 在一些实施例中，第二层是功函数金属，第一层是电介质。 在一些实施例中，第二层是阻挡层。
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公开(公告)号：US20150380412A1
公开(公告)日：2015-12-31
申请号：US14844809
申请日：2015-09-03
IPC分类号： H01L27/092 , H01L29/06 , H01L29/78 , H01L21/8238 , H01L29/66
CPC分类号： H01L27/0924 , H01L21/823807 , H01L21/823814 , H01L21/823821 , H01L21/823828 , H01L21/823864 , H01L21/823878 , H01L27/0922 , H01L29/0653 , H01L29/1054 , H01L29/16 , H01L29/165 , H01L29/66477 , H01L29/66545 , H01L29/66795 , H01L29/7848 , H01L29/785
摘要： Embodiments of the present disclosure are a FinFET device, and methods of forming a FinFET device. An embodiment is a method for forming a FinFET device, the method comprising forming a semiconductor strip over a semiconductor substrate, wherein the semiconductor strip is disposed in a dielectric layer, forming a gate over the semiconductor strip and the dielectric layer, and forming a first recess and a second recess in the semiconductor strip, wherein the first recess is on an opposite side of the gate from the second recess. The method further comprises forming a source region in the first recess and a drain region in the second recess, and recessing the dielectric layer, wherein a first portion of the semiconductor strip extends above a top surface of the dielectric layer forming a semiconductor fin.
摘要翻译： 本公开的实施例是FinFET器件，以及形成FinFET器件的方法。 一个实施例是一种用于形成FinFET器件的方法，该方法包括在半导体衬底上形成半导体条，其中半导体条布置在电介质层中，在半导体条和电介质层上形成栅极，并形成第一 凹部和半导体条中的第二凹部，其中第一凹部位于与第二凹部的栅极相反的一侧。 所述方法还包括在所述第一凹槽中形成源极区域和在所述第二凹槽中形成漏极区域，以及使所述电介质层凹陷，其中所述半导体薄膜的第一部分在形成半导体鳍片的介电层的顶表面上方延伸。
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公开(公告)号：US09048253B2
公开(公告)日：2015-06-02
申请号：US14040224
申请日：2013-09-27
发明人： Chun-Feng Nieh , Ming-Huan Tsai , Wei-Han Fan , Yimin Huang , Chun-Fai Cheng , Han-Ting Tsai , Chii-Ming Wu
IPC分类号： H01L21/336 , H01L29/66 , H01L21/8238 , H01L29/78
CPC分类号： H01L21/823814 , H01L21/26586 , H01L21/30604 , H01L21/3065 , H01L21/76224 , H01L21/823807 , H01L21/823878 , H01L29/66492 , H01L29/6659 , H01L29/66636 , H01L29/7834 , H01L29/7848
摘要： An integrated circuit device and method for manufacturing the integrated circuit device is disclosed. The disclosed method provides improved control over a surface proximity and tip depth of an integrated circuit device. In an embodiment, the method achieves improved control by forming a doped region and a lightly doped source and drain (LDD) region in a source and drain region of the device. The doped region is implanted with a dopant type opposite to the LDD region.
摘要翻译： 公开了一种用于制造集成电路器件的集成电路器件和方法。 所公开的方法提供对集成电路器件的表面接近度和尖端深度的改进的控制。 在一个实施例中，该方法通过在器件的源极和漏极区域中形成掺杂区域和轻掺杂源极和漏极（LDD）区域来实现改进的控制。 掺杂区域注入与LDD区域相反的掺杂剂类型。
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公开(公告)号：US20140239354A1
公开(公告)日：2014-08-28
申请号：US13779356
申请日：2013-02-27
发明人： Yu-Lien Huang , Chun-Hsiang Fan , Tsu-Hsiu Perng , Chi-Kang Liu , Yung-Ta Li , Ming-Huan Tsai , Clement Hsingjen Wann , Chi-Wen Liu
IPC分类号： H01L29/78
CPC分类号： H01L29/66795 , H01L21/30604 , H01L21/3247 , H01L29/0653 , H01L29/34 , H01L29/66545 , H01L29/6681 , H01L29/7853
摘要： A finFET and methods for forming a finFET are disclosed. A structure comprises a substrate, a fin, a gate dielectric, and a gate electrode. The substrate comprises the fin. The fin has a major surface portion of a sidewall, and the major surface portion comprises at least one lattice shift. The at least one lattice shift comprises an inward or outward shift relative to a center of the fin. The gate dielectric is on the major surface portion of the sidewall. The gate electrode is on the gate dielectric.
摘要翻译： 公开了一种finFET和用于形成finFET的方法。 一种结构包括衬底，翅片，栅极电介质和栅电极。 基板包括翅片。 翅片具有侧壁的主表面部分，并且主表面部分包括至少一个晶格位移。 至少一个晶格位移包括相对于鳍的中心的向内或向外移动。 栅极电介质位于侧壁的主表面部分上。 栅极电极位于栅极电介质上。
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公开(公告)号：US20140203333A1
公开(公告)日：2014-07-24
申请号：US13745205
申请日：2013-01-18
CPC分类号： H01L29/4966 , H01L21/02697 , H01L29/42368 , H01L29/42376 , H01L29/517 , H01L29/66545 , H01L29/78 , H01L29/7833
摘要： In one embodiment, a method includes providing a semiconductor substrate having a trench disposed thereon and forming a plurality of layers in the trench. The plurality of layers formed in the trench is etched thereby providing at least one etched layer having a top surface that lies below a top surface of the trench. In a further embodiment, this may provide for a substantially v-shaped opening or entry to the trench for the formation of further layers. Further, a device having a modified profile metal gate for example having at least one layer of the metal.
摘要翻译： 在一个实施例中，一种方法包括提供其上设置有沟槽并在沟槽中形成多个层的半导体衬底。 蚀刻形成在沟槽中的多个层，从而提供至少一个具有位于沟槽顶表面下方的顶表面的蚀刻层。 在另一个实施例中，这可以提供用于形成另外的层的大致v形的开口或沟槽的入口。 此外，具有例如具有至少一层金属的改性型材金属栅极的器件。
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公开(公告)号：US20140024188A1
公开(公告)日：2014-01-23
申请号：US14040224
申请日：2013-09-27
发明人： Chun-Feng Nieh , Ming-Huan Tsai , Wei-Han Fan , Yimin Huang , Chun-Fai Cheng , Han-Ting Tsai , Chii-Ming Wu
IPC分类号： H01L29/66
CPC分类号： H01L21/823814 , H01L21/26586 , H01L21/30604 , H01L21/3065 , H01L21/76224 , H01L21/823807 , H01L21/823878 , H01L29/66492 , H01L29/6659 , H01L29/66636 , H01L29/7834 , H01L29/7848
摘要： An integrated circuit device and method for manufacturing the integrated circuit device is disclosed. The disclosed method provides improved control over a surface proximity and tip depth of an integrated circuit device. In an embodiment, the method achieves improved control by forming a doped region and a lightly doped source and drain (LDD) region in a source and drain region of the device. The doped region is implanted with a dopant type opposite to the LDD region.
摘要翻译： 公开了一种用于制造集成电路器件的集成电路器件和方法。 所公开的方法提供对集成电路器件的表面接近度和尖端深度的改进的控制。 在一个实施例中，该方法通过在器件的源极和漏极区域中形成掺杂区域和轻掺杂源极和漏极（LDD）区域来实现改进的控制。 掺杂区域注入与LDD区域相反的掺杂剂类型。
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公开(公告)号：US09887274B2
公开(公告)日：2018-02-06
申请号：US15144360
申请日：2016-05-02
发明人： Yu-Lien Huang , Chun-Hsiang Fan , Tsu-Hsiu Perng , Chi-Kang Liu , Yung-Ta Li , Ming-Huan Tsai , Clement Hsingjen Wann , Chi-Wen Liu
IPC分类号： H01L29/66 , H01L29/78 , H01L29/34 , H01L21/306 , H01L21/324 , H01L29/06
CPC分类号： H01L29/66795 , H01L21/30604 , H01L21/3247 , H01L29/0653 , H01L29/34 , H01L29/66545 , H01L29/6681 , H01L29/7853
摘要： A FinFET and methods for forming a FinFET are disclosed. A method includes forming trenches in a semiconductor substrate to form a fin, depositing an insulating material within the trenches, and removing a portion of the insulating material to expose sidewalls of the fin. The method also includes recessing a portion of the exposed sidewalls of the fin to form multiple recessed surfaces on the exposed sidewalls of the fin, wherein adjacent recessed surfaces of the multiple recessed surfaces are separated by a lattice shift. The method also includes depositing a gate dielectric on the recessed portion of the sidewalls of the fin and depositing a gate electrode on the gate dielectric.
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9.发明授权High performance strained source-drain structure and method of fabricating the same 有权高性能应变源极 - 漏极结构及其制造方法公开(公告)号：US09293537B2
公开(公告)日：2016-03-22
申请号：US14261570
申请日：2014-04-25
IPC分类号： H01L29/78 , H01L29/165 , H01L21/265 , H01L21/8234 , H01L21/8238 , H01L29/66
CPC分类号： H01L29/165 , H01L21/26586 , H01L21/823412 , H01L21/823418 , H01L21/823807 , H01L21/823814 , H01L29/66628 , H01L29/66636 , H01L29/7848
摘要： A method for forming a high performance strained source-drain structure includes forming a gate structure on a substrate and forming a pocket implant region proximate to the gate structure. Spacers are formed adjacent to the gate structure. A dry etch forms a recess with a first contour; a wet etch enlarge the recess to a second contour; and a thermal etch enlarges the recess to a third contour. The source-drain structure is then formed in the recess having the third contour.
摘要翻译： 用于形成高性能应变源极 - 漏极结构的方法包括在衬底上形成栅极结构并且形成靠近栅极结构的凹穴注入区域。 隔板与门结构相邻形成。 干蚀刻形成具有第一轮廓的凹部; 湿蚀刻将凹槽放大到第二轮廓; 并且热蚀刻将凹槽放大到第三轮廓。 然后在具有第三轮廓的凹槽中形成源极 - 漏极结构。
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公开(公告)号：US09257323B2
公开(公告)日：2016-02-09
申请号：US13894605
申请日：2013-05-15
发明人： Yu-Lien Huang , Tung Ying Lee , Pei-Yi Lin , Chun-Hsiang Fan , Sheng-Wen Yu , Neng-Kuo Chen , Ming-Huan Tsai
IPC分类号： H01L21/70 , H01L21/762
CPC分类号： H01L21/823481 , H01L21/31055 , H01L21/324 , H01L21/76224 , H01L21/76229 , H01L27/088 , H01L29/401
摘要： A semiconductor device includes a substrate and a gate structure formed over the substrate. The semiconductor device further includes an insulator feature formed in the substrate. The insulator feature includes an insulating layer and a capping layer over the insulating layer.
摘要翻译： 半导体器件包括衬底和形成在衬底上的栅极结构。 半导体器件还包括形成在衬底中的绝缘体特征。 绝缘体特征包括在绝缘层上的绝缘层和覆盖层。
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