公开(公告)号：US11672110B2

公开(公告)日：2023-06-06

申请号：US17216161

申请日：2021-03-29

申请人： Taiwan Semiconductor Manufacturing Company Limited

发明人： Gerben Doornbos ,  Blandine Duriez ,  Marcus Johannes Henricus Van Dal

IPC分类号： H01L29/786 ,  H01L27/108 ,  H01L29/78 ,  H01L29/66 ,  H01L29/225 ,  H01L29/06

CPC分类号： H01L27/10852 ,  H01L27/10805 ,  H01L27/10814 ,  H01L27/10885 ,  H01L29/0673 ,  H01L29/225 ,  H01L29/66742 ,  H01L29/785 ,  H01L29/7869 ,  H01L29/78642 ,  H01L29/78696 ,  H01L2029/7858

摘要： A semiconductor transistor comprises a channel structure comprising a channel region and two source/drain regions located on respective sides of the channel region, wherein the channel region and the two source/drain regions are stacked up along a first direction. A gate structure surrounds the channel region.

公开(公告)号：US20150295064A1

公开(公告)日：2015-10-15

申请号：US14249397

申请日：2014-04-10

申请人： Taiwan Semiconductor Manufacturing Company Limited

发明人： Mark van Dal ,  Blandine Duriez

IPC分类号： H01L29/66 ,  H01L29/78

CPC分类号： H01L21/823431 ,  H01L21/3065 ,  H01L21/823412 ,  H01L21/823437 ,  H01L21/823462 ,  H01L29/1037 ,  H01L29/1054 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/7853

摘要： A semiconductor device and methods of formation are provided. The semiconductor device includes a first active region having a first active region height and an active channel region having an active channel region height over a fin. The first active region height is greater than the active channel region height. The active channel region having the active channel region height has increased strain, such as increased tensile strain, as compared to an active channel region that has a height greater than the active channel region height. The increased strain increases or enhances at least one of hole mobility or electron mobility in at least one of the first active region or the active channel region. The active channel region having the active channel region height has decreased source drain leakage, as compared to an active channel region that has a height greater than the active channel region height.

摘要翻译： 提供半导体器件和形成方法。 半导体器件包括具有第一有源区高度的第一有源区和在鳍上方具有有源沟道区高度的有源沟道区。 第一有源区高度大于有源沟道区高度。 与具有高于有源沟道区高度的有源沟道区相比，具有有源沟道区高度的有源沟道区具有增加的应变，例如增加的拉伸应变。 增加的应变增加或增强至少一个第一有源区或有源沟道区中的空穴迁移率或电子迁移率中的至少一个。 与具有大于有源沟道区高度的高度的有源沟道区相比，具有有源沟道区高度的有源沟道区具有减小的源极漏极泄漏。

公开(公告)号：US20170033014A1

公开(公告)日：2017-02-02

申请号：US15270207

申请日：2016-09-20

申请人： Taiwan Semiconductor Manufacturing Company Limited

发明人： Mark van Dal ,  Blandine Duriez

IPC分类号： H01L21/8234 ,  H01L29/66 ,  H01L21/3065 ,  H01L29/78 ,  H01L29/10

CPC分类号： H01L21/823431 ,  H01L21/3065 ,  H01L21/823412 ,  H01L21/823437 ,  H01L21/823462 ,  H01L29/1037 ,  H01L29/1054 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/7853

摘要： A semiconductor device and methods of formation are provided. The semiconductor device includes a first active region having a first active region height and an active channel region having an active channel region height over a fin. The first active region height is greater than the active channel region height. The active channel region having the active channel region height has increased strain, such as increased tensile strain, as compared to an active channel region that has a height greater than the active channel region height. The increased strain increases or enhances at least one of hole mobility or electron mobility in at least one of the first active region or the active channel region. The active channel region having the active channel region height has decreased source drain leakage, as compared to an active channel region that has a height greater than the active channel region height.

摘要翻译： 提供半导体器件和形成方法。 半导体器件包括具有第一有源区高度的第一有源区和在鳍上方具有有源沟道区高度的有源沟道区。 第一有源区高度大于有源沟道区高度。 与具有高于有源沟道区高度的有源沟道区相比，具有有源沟道区高度的有源沟道区具有增加的应变，例如增加的拉伸应变。 增加的应变增加或增强至少一个第一有源区或有源沟道区中的空穴迁移率或电子迁移率中的至少一个。 与具有大于有源沟道区高度的高度的有源沟道区相比，具有有源沟道区高度的有源沟道区具有减小的源极漏极泄漏。

公开(公告)号：US11942147B2

公开(公告)日：2024-03-26

申请号：US17872111

申请日：2022-07-25

申请人： Taiwan Semiconductor Manufacturing Company Limited

发明人： Marcus Johannes Henricus Van Dal ,  Gerben Doornbos ,  Georgios Vellianitis ,  Blandine Duriez ,  Mauricio Manfrini

IPC分类号： G11C11/00 ,  G11C13/00 ,  H10B63/00 ,  H10N70/00 ,  H10N70/20

CPC分类号： G11C13/0007 ,  G11C13/0069 ,  H10B63/34 ,  H10B63/80 ,  H10N70/011 ,  H10N70/253 ,  H10N70/841 ,  H10N70/8833

摘要： A memory device is provided, which may include a first electrode, a memory layer stack including at least one semiconducting metal oxide layer and at least one hydrogen-containing metal layer, and a second electrode. A semiconductor device is provided, which may include a semiconducting metal oxide layer containing a source region, a drain region, and a channel region, a hydrogen-containing metal layer located on a surface of the channel region, and a gate electrode located on the hydrogen-containing metal layer. Each hydrogen-containing metal layer may include at least one metal selected from platinum, iridium, osmium, and ruthenium at an atomic percentage that is at least 90%, and may include hydrogen atoms at an atomic percentage in a range from 0.001% to 10%. Hydrogen atoms may be reversibly impregnated into a respective semiconducting metal oxide layer to change resistivity and to encode a memory bit.

公开(公告)号：US20210376156A1

公开(公告)日：2021-12-02

申请号：US17215997

申请日：2021-03-29

申请人： Taiwan Semiconductor Manufacturing Company Limited

发明人： Gerben Doornbos ,  Blandine Duriez ,  Marcus Johannes Henricus van Dal

IPC分类号： H01L29/786 ,  H01L29/66

摘要： A transistor, integrated semiconductor device and methods of making. The transistor includes a patterned gate electrode, a dielectric layer located over the patterned gate electrode and a patterned first oxide semiconductor layer comprising a channel region and source/drain regions located on sides of the channel region. The thickness of the source/drain regions is greater than a thickness of the channel region. The transistor also includes contacts located on the patterned first oxide semiconductor layer and connected to the source/drain regions of the patterned first oxide semiconductor layer.

公开(公告)号：US09698240B2

公开(公告)日：2017-07-04

申请号：US14230203

申请日：2014-03-31

申请人： Taiwan Semiconductor Manufacturing Company Limited

发明人： Blandine Duriez ,  Mark van Dal

IPC分类号： H01L29/66 ,  H01L29/78

CPC分类号： H01L29/66545 ,  H01L29/41791 ,  H01L29/42392 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/78696

摘要： A semiconductor device and methods of formation are provided. The semiconductor device includes a gate over a channel portion of a fin. The fin includes a first active area of the fin having a first active area top surface coplanar with a first shallow trench isolation (STI) top surface of a first STI portion of STI, and a second active area of the fin having a second active area top surface coplanar with a second STI top surface of a second STI portion of the STI. The method herein negates a need to recess at least one of the fin, the first STI portion or the second STI portion during device formation. Negating a need to recess at least one of the fin, the first STI portion or the second STI portion enhances the semiconductor device formation and is more efficient than a semiconductor device formation that requires the recessing of at least one of a fin, a first STI portion or a second STI portion.

公开(公告)号：US11430512B2

公开(公告)日：2022-08-30

申请号：US17229748

申请日：2021-04-13

申请人： Taiwan Semiconductor Manufacturing Company Limited

发明人： Marcus Johannes Henricus Van Dal ,  Gerben Doornbos ,  Georgios Vellianitis ,  Blandine Duriez ,  Mauricio Manfrini

IPC分类号： G11C11/00 ,  G11C13/00 ,  H01L27/24 ,  H01L45/00

摘要： A memory device is provided, which may include a first electrode, a memory layer stack including at least one semiconducting metal oxide layer and at least one hydrogen-containing metal layer, and a second electrode. A semiconductor device is provided, which may include a semiconducting metal oxide layer containing a source region, a drain region, and a channel region, a hydrogen-containing metal layer located on a surface of the channel region, and a gate electrode located on the hydrogen-containing metal layer. Each hydrogen-containing metal layer may include at least one metal selected from platinum, iridium, osmium, and ruthenium at an atomic percentage that is at least 90%, and may include hydrogen atoms at an atomic percentage in a range from 0.001% to 10%. Hydrogen atoms may be reversibly impregnated into a respective semiconducting metal oxide layer to change resistivity and to encode a memory bit.

公开(公告)号：US09991169B2

公开(公告)日：2018-06-05

申请号：US15270207

申请日：2016-09-20

申请人： Taiwan Semiconductor Manufacturing Company Limited

发明人： Mark van Dal ,  Blandine Duriez

IPC分类号： H01L21/8234 ,  H01L29/78 ,  H01L29/66 ,  H01L29/10 ,  H01L21/3065

CPC分类号： H01L21/823431 ,  H01L21/3065 ,  H01L21/823412 ,  H01L21/823437 ,  H01L21/823462 ,  H01L29/1037 ,  H01L29/1054 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/7853

摘要： A semiconductor device and methods of formation are provided. The semiconductor device includes a first active region having a first active region height and an active channel region having an active channel region height over a fin. The first active region height is greater than the active channel region height. The active channel region having the active channel region height has increased strain, such as increased tensile strain, as compared to an active channel region that has a height greater than the active channel region height. The increased strain increases or enhances at least one of hole mobility or electron mobility in at least one of the first active region or the active channel region. The active channel region having the active channel region height has decreased source drain leakage, as compared to an active channel region that has a height greater than the active channel region height.

公开(公告)号：US20150279964A1

公开(公告)日：2015-10-01

申请号：US14230203

申请日：2014-03-31

申请人： Taiwan Semiconductor Manufacturing Company Limited

发明人： Blandine Duriez ,  Mark van Dal

IPC分类号： H01L29/66 ,  H01L29/78

CPC分类号： H01L29/66545 ,  H01L29/41791 ,  H01L29/42392 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/78696

摘要： A semiconductor device and methods of formation are provided. The semiconductor device includes a gate over a channel portion of a fin. The fin includes a first active area of the fin having a first active area top surface coplanar with a first shallow trench isolation (STI) top surface of a first STI portion of STI, and a second active area of the fin having a second active area top surface coplanar with a second STI top surface of a second STI portion of the STI. The method herein negates a need to recess at least one of the fin, the first STI portion or the second STI portion during device formation. Negating a need to recess at least one of the fin, the first STI portion or the second STI portion enhances the semiconductor device formation and is more efficient than a semiconductor device formation that requires the recessing of at least one of a fin, a first STI portion or a second STI portion.

摘要翻译： 提供半导体器件和形成方法。 半导体器件包括在鳍的通道部分上的栅极。 翅片包括翅片的第一有源区域，其具有与STI的第一STI部分的第一浅沟槽隔离（STI）顶表面共面的第一有源区顶表面，并且鳍的第二有源区具有第二有源区 顶表面与STI的第二STI部分的第二STI顶表面共面。 该方法在装置形成期间不需要在翅片，第一STI部分或第二STI部分中的至少一个凹陷。 不需要凹陷翅片，第一STI部分或第二STI部分中的至少一个，增强了半导体器件形成，并且比需要半翅片，第一STI的至少一个的半导体器件形成更有效 部分或第二STI部分。

公开(公告)号：US20230387314A1

公开(公告)日：2023-11-30

申请号：US18366725

申请日：2023-08-08

申请人： Taiwan Semiconductor Manufacturing Company Limited

发明人： Gerben Doornbos ,  Blandine Duriez ,  Marcus Johannes Henricus Van Dal

IPC分类号： H01L29/786 ,  H01L29/66

CPC分类号： H01L29/78618 ,  H01L29/7869 ,  H01L29/66969 ,  H01L29/267

摘要： A transistor, integrated semiconductor device and methods of making are disclosed. The transistor includes a patterned gate electrode, a dielectric layer located over the patterned gate electrode and a patterned first oxide semiconductor layer comprising a channel region and source/drain regions located on sides of the channel region. The thickness of the source/drain regions is greater than a thickness of the channel region. The transistor also includes contacts located on the patterned first oxide semiconductor layer and connected to the source/drain regions of the patterned first oxide semiconductor layer.