公开(公告)号：US09361980B1

公开(公告)日：2016-06-07

申请号：US14620352

申请日：2015-02-12

Applicant: Taiwan Semiconductor Manufacturing Company Limited

Inventor： Chun-Yang Tsai ,  Hon-Jarn Lin ,  Kuo-Ching Huang ,  Yu-Wei Ting

IPC: G11C11/00 ,  G11C13/00

CPC classification number: G11C13/0097 ,  G11C8/08 ,  G11C13/0028 ,  G11C13/0064 ,  G11C13/0069 ,  G11C2013/0066 ,  G11C2013/0071 ,  G11C2213/79 ,  G11C2213/82

Abstract: According to another embodiment, a method of reset operation for a resistive random access memory (RRAM) array, having a first RRAM connected to a first word line and a second RRAM connected to a second word line, is provided. A first electrical resistance between the first word line and a word line voltage source is lower than a second electrical resistance between the second word line and the word line voltage source. The method includes: providing a first voltage by using the word line voltage source for resetting the first RRAM; and providing a second voltage by using the word line voltage source for resetting the second RRAM, wherein the first voltage for resetting the first RRAM is lower than the second voltage for resetting the second RRAM.

Abstract translation: 根据另一实施例，提供一种具有连接到第一字线的第一RRAM和连接到第二字线的第二RRAM的电阻随机存取存储器（RRAM）阵列的复位操作的方法。 第一字线和字线电压源之间的第一电阻低于第二字线和字线电压源之间的第二电阻。 该方法包括：通过使用用于复位第一RRAM的字线电压源来提供第一电压; 以及通过使用用于复位第二RRAM的字线电压源来提供第二电压，其中用于复位第一RRAM的第一电压低于用于复位第二RRAM的第二电压。

公开(公告)号：US10319423B2

公开(公告)日：2019-06-11

申请号：US15800700

申请日：2017-11-01

Applicant: Taiwan Semiconductor Manufacturing Company Limited

Inventor： Chia-Fu Lee ,  Hon-Jarn Lin ,  Yu-Der Chih

IPC: G11C11/16 ,  G11C7/06 ,  G11C11/15 ,  H01L43/02 ,  G11C7/14

Abstract: A memory device includes a memory cell unit, a reference circuit, and a sense amplifier. The memory cell unit includes a memory cell. The reference circuit is configured to generate a reference current and includes a plurality of magnetic resistive elements. At least one of the magnetic resistive elements is in a high resistance state. The sense amplifier is coupled to the memory cell unit and the reference circuit and is configured to compare a current that flows through the memory cell to the reference current to sense a bit of data stored in the memory cell, to amplify a level of the sensed bit of data, and to output the amplified bit of data.

公开(公告)号：US20180151211A1

公开(公告)日：2018-05-31

申请号：US15800700

申请日：2017-11-01

Applicant: Taiwan Semiconductor Manufacturing Company Limited

Inventor： Chia-Fu Lee ,  Hon-Jarn Lin ,  Yu-Der Chih

IPC: G11C11/16 ,  G11C7/06 ,  G11C11/15 ,  H01L43/02

CPC classification number: G11C11/161 ,  G11C7/06 ,  G11C7/062 ,  G11C7/14 ,  G11C11/15 ,  G11C11/1673 ,  G11C11/1675 ,  G11C2207/063 ,  H01L43/02

Abstract: A memory device includes a memory cell unit, a reference circuit, and a sense amplifier. The memory cell unit includes a memory cell. The reference circuit is configured to generate a reference current and includes a plurality of magnetic resistive elements. At least one of the magnetic resistive elements is in a high resistance state. The sense amplifier is coupled to the memory cell unit and the reference circuit and is configured to compare a current that flows through the memory cell to the reference current to sense a bit of data stored in the memory cell, to amplify a level of the sensed bit of data, and to output the amplified bit of data.