公开(公告)号：US09805980B2

公开(公告)日：2017-10-31

申请号：US14995185

申请日：2016-01-13

申请人： Renesas Electronics Corporation

发明人： Tadashi Munakata ,  Shingo Oosaka ,  Mitsuru Kinoshita ,  Yoshihiko Yamaguchi ,  Noriyuki Takahashi

IPC分类号： H01L21/78 ,  H01L21/56 ,  H01L21/67 ,  H01L23/00 ,  H01L21/02 ,  H01L21/673 ,  H01L21/683 ,  H01L23/31

CPC分类号： H01L21/78 ,  H01L21/02076 ,  H01L21/561 ,  H01L21/565 ,  H01L21/67092 ,  H01L21/67126 ,  H01L21/67333 ,  H01L21/6838 ,  H01L23/3128 ,  H01L24/73 ,  H01L24/97 ,  H01L2224/32225 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48225 ,  H01L2224/48227 ,  H01L2224/48465 ,  H01L2224/73265 ,  H01L2224/97 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01009 ,  H01L2924/01033 ,  H01L2924/01039 ,  H01L2924/01057 ,  H01L2924/01075 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/15183 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/3025 ,  H01L2224/85 ,  H01L2924/00014 ,  H01L2224/83 ,  H01L2924/00012 ,  H01L2924/00

摘要： A semiconductor device manufacturing method comprising the steps of providing a matrix substrate having a main surface with plural device areas formed thereon, fixing plural semiconductor chips to the plural device areas respectively, then sealing the plural semiconductor chips all together with resin to form a block sealing member, dividing the block sealing member and the matrix substrate for each of the device areas by dicing, thereafter rubbing a surface of each of the diced sealing member portions with a brush, then storing semiconductor devices formed by the dicing once into pockets respectively of a tray, and conveying the semiconductor devices each individually from the tray. Since the substrate dividing work after block molding is performed by dicing while vacuum-chucking the surface of the block sealing member, the substrate division can be done without imposing any stress on an external terminal mounting surface of the matrix substrate.

公开(公告)号：US09673167B2

公开(公告)日：2017-06-06

申请号：US14416297

申请日：2012-07-26

申请人： Markus Wimplinger

发明人： Markus Wimplinger

IPC分类号： H01L23/00 ,  H01L31/18 ,  B32B37/24 ,  B32B38/00 ,  C23C14/08 ,  C23C16/40

CPC分类号： H01L24/83 ,  B32B37/24 ,  B32B38/0008 ,  B32B2037/243 ,  B32B2037/246 ,  B32B2457/14 ,  C23C14/08 ,  C23C14/081 ,  C23C14/086 ,  C23C16/40 ,  C23C16/403 ,  C23C16/407 ,  H01L24/27 ,  H01L24/29 ,  H01L24/32 ,  H01L24/75 ,  H01L31/18 ,  H01L2224/2741 ,  H01L2224/27418 ,  H01L2224/2745 ,  H01L2224/27452 ,  H01L2224/278 ,  H01L2224/27848 ,  H01L2224/2908 ,  H01L2224/29187 ,  H01L2224/29287 ,  H01L2224/29394 ,  H01L2224/29395 ,  H01L2224/3201 ,  H01L2224/32145 ,  H01L2224/32501 ,  H01L2224/7501 ,  H01L2224/75101 ,  H01L2224/83001 ,  H01L2224/83002 ,  H01L2224/83011 ,  H01L2224/83012 ,  H01L2224/83013 ,  H01L2224/83065 ,  H01L2224/83075 ,  H01L2224/8322 ,  H01L2224/8383 ,  H01L2224/83896 ,  H01L2224/83907 ,  H01L2924/01009 ,  H01L2924/01013 ,  H01L2924/0103 ,  H01L2924/01031 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/01051 ,  H01L2924/053 ,  H01L2924/12042 ,  H01L2924/20102 ,  H01L2924/0549 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2924/0531 ,  H01L2924/01001 ,  H01L2924/01008 ,  H01L2924/00

摘要： This invention relates to a method for bonding of a first contact area of a first at least largely transparent substrate to a second contact area of a second at least largely transparent substrate, on at least one of the contact areas an oxide being used for bonding, from which an at least largely transparent interconnection layer is formed with an electrical conductivity of at least 10e1 S/cm2 (measurement: four point method, relative to temperature of 300K) and an optical transmittance greater than 0.8 (for a wavelength range from 400 nm to 1500 nm) on the first and second contact area.

公开(公告)号：US20150170964A1

公开(公告)日：2015-06-18

申请号：US14108819

申请日：2013-12-17

申请人： Taiwan Semiconductor Manufacturing Company Limited

发明人： CHI-YUAN CHEN ,  LI-TING WANG ,  TENG-CHUN TSAI ,  CHUN-I TSAI ,  WEI-JUNG LIN ,  HUANG-YI HUANG ,  CHENG-TUNG LIN ,  HONG-MAO LEE

IPC分类号： H01L21/768 ,  C23C14/58 ,  C23C14/48

CPC分类号： H01L21/02694 ,  C23C14/046 ,  C23C14/48 ,  C23C14/5873 ,  H01L21/02697 ,  H01L21/0415 ,  H01L21/046 ,  H01L21/2253 ,  H01L21/31155 ,  H01L21/32134 ,  H01L21/32135 ,  H01L21/3215 ,  H01L21/76224 ,  H01L21/76254 ,  H01L21/76859 ,  H01L21/76876 ,  H01L21/76877 ,  H01L21/76879 ,  H01L29/66734 ,  H01L2224/05157 ,  H01L2924/01002 ,  H01L2924/01007 ,  H01L2924/01009 ,  H01L2924/01022 ,  H01L2924/01074

摘要： Systems and methods are provided for contact formation. A semiconductor structure is provided. The semiconductor structure includes an opening formed by a bottom surface and one or more side surfaces. A first conductive material is formed on the bottom surface and the one or more side surfaces to partially fill the opening, the first conductive material including a top portion and a bottom portion. Ion implantation is formed on the first conductive material, the top portion of the first conductive material being associated with a first ion density, the bottom portion of the first conductive material being associated with a second ion density lower than the first ion density. At least part of the top portion of the first conductive material is removed. A second conductive material is formed to fill the opening.

摘要翻译： 为接触形成提供了系统和方法。 提供半导体结构。 半导体结构包括由底表面和一个或多个侧表面形成的开口。 第一导电材料形成在底表面和一个或多个侧表面上以部分地填充开口，第一导电材料包括顶部和底部。 在第一导电材料上形成离子注入，第一导电材料的顶部与第一离子密度相关联，第一导电材料的底部与低于第一离子密度的第二离子密度相关联。 去除第一导电材料的顶部的至少一部分。 形成第二导电材料以填充开口。

公开(公告)号：US08916871B2

公开(公告)日：2014-12-23

申请号：US13611467

申请日：2012-09-12

申请人： Brian Joel Alvarez ,  Donald R. Disney ,  Hui Nie ,  Patrick James Lazlo Hyland

发明人： Brian Joel Alvarez ,  Donald R. Disney ,  Hui Nie ,  Patrick James Lazlo Hyland

IPC分类号： H01L29/10 ,  H01L23/48

CPC分类号： H01L29/2003 ,  H01L21/28575 ,  H01L21/28581 ,  H01L23/4827 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L24/09 ,  H01L24/27 ,  H01L24/29 ,  H01L24/32 ,  H01L24/40 ,  H01L24/45 ,  H01L24/48 ,  H01L24/83 ,  H01L24/84 ,  H01L24/85 ,  H01L24/92 ,  H01L29/417 ,  H01L29/41741 ,  H01L29/452 ,  H01L29/475 ,  H01L29/4958 ,  H01L29/861 ,  H01L29/872 ,  H01L2224/0345 ,  H01L2224/03462 ,  H01L2224/0348 ,  H01L2224/03614 ,  H01L2224/03622 ,  H01L2224/03848 ,  H01L2224/04034 ,  H01L2224/04042 ,  H01L2224/05082 ,  H01L2224/05083 ,  H01L2224/05124 ,  H01L2224/05144 ,  H01L2224/05155 ,  H01L2224/05164 ,  H01L2224/05166 ,  H01L2224/05169 ,  H01L2224/05171 ,  H01L2224/0518 ,  H01L2224/05184 ,  H01L2224/05187 ,  H01L2224/05541 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05664 ,  H01L2224/05669 ,  H01L2224/06181 ,  H01L2224/09181 ,  H01L2224/2732 ,  H01L2224/27436 ,  H01L2224/291 ,  H01L2224/29116 ,  H01L2224/29144 ,  H01L2224/32245 ,  H01L2224/45015 ,  H01L2224/45124 ,  H01L2224/48724 ,  H01L2224/48739 ,  H01L2224/48744 ,  H01L2224/48747 ,  H01L2224/48755 ,  H01L2224/48764 ,  H01L2224/48769 ,  H01L2224/73265 ,  H01L2224/83191 ,  H01L2224/83192 ,  H01L2224/83801 ,  H01L2224/83815 ,  H01L2224/9202 ,  H01L2224/9221 ,  H01L2224/92242 ,  H01L2224/92247 ,  H01L2924/00014 ,  H01L2924/1033 ,  H01L2924/12032 ,  H01L2924/1305 ,  H01L2924/13062 ,  H01L2924/13063 ,  H01L2924/13091 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2924/014 ,  H01L2924/0105 ,  H01L2924/01047 ,  H01L2924/01009 ,  H01L2224/03 ,  H01L2224/83 ,  H01L2224/85 ,  H01L2224/84 ,  H01L2924/04941 ,  H01L2224/37099 ,  H01L2224/37599

摘要： An embodiment of a semiconductor device includes a gallium nitride (GaN) substrate having a first surface and a second surface. The second surface is substantially opposite the first surface, at least one device layer is coupled to the first surface, and a backside metal is coupled to the second surface. A top metal stack is coupled to the at least one device layer. The top metal stack includes a contact metal coupled to a surface of the at least one device layer, a protection layer coupled to the contact metal, a diffusion barrier coupled to the protection layer, and a pad metal coupled to the diffusion barrier. The semiconductor device is configured to conduct electricity between the top metal stack and the backside metal.

摘要翻译： 半导体器件的实施例包括具有第一表面和第二表面的氮化镓（GaN）衬底。 第二表面基本上与第一表面相对，至少一个器件层耦合到第一表面，并且背面金属耦合到第二表面。 顶部金属叠层耦合到至少一个器件层。 顶部金属堆叠包括耦合到至少一个器件层的表面的接触金属，耦合到接触金属的保护层，耦合到保护层的扩散阻挡层以及耦合到扩散阻挡层的焊盘金属。 半导体器件被配置为在顶部金属堆叠和背面金属之间导电。

公开(公告)号：US08877613B2

公开(公告)日：2014-11-04

申请号：US12894987

申请日：2010-09-30

申请人： Tadashi Munakata ,  Shingo Oosaka ,  Mitsuru Kinoshita ,  Yoshihiko Yamaguchi ,  Noriyuki Takahashi

发明人： Tadashi Munakata ,  Shingo Oosaka ,  Mitsuru Kinoshita ,  Yoshihiko Yamaguchi ,  Noriyuki Takahashi

IPC分类号： H01L21/02 ,  H01L23/00 ,  H01L21/56 ,  H01L21/67 ,  H01L23/31

CPC分类号： H01L21/78 ,  H01L21/02076 ,  H01L21/561 ,  H01L21/565 ,  H01L21/67092 ,  H01L21/67126 ,  H01L21/67333 ,  H01L21/6838 ,  H01L23/3128 ,  H01L24/73 ,  H01L24/97 ,  H01L2224/32225 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48225 ,  H01L2224/48227 ,  H01L2224/48465 ,  H01L2224/73265 ,  H01L2224/97 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01009 ,  H01L2924/01033 ,  H01L2924/01039 ,  H01L2924/01057 ,  H01L2924/01075 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/15183 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/3025 ,  H01L2224/85 ,  H01L2924/00014 ,  H01L2224/83 ,  H01L2924/00012 ,  H01L2924/00

摘要： A semiconductor device manufacturing method comprising the steps of providing a matrix substrate having a main surface with plural device areas formed thereon, fixing plural semiconductor chips to the plural device areas respectively, then sealing the plural semiconductor chips all together with resin to form a block sealing member, dividing the block sealing member and the matrix substrate for each of the device areas by dicing, thereafter rubbing a surface of each of the diced sealing member portions with a brush, then storing semiconductor devices formed by the dicing once into pockets respectively of a tray, and conveying the semiconductor devices each individually from the tray. Since the substrate dividing work after block molding is performed by dicing while vacuum-chucking the surface of the block sealing member, the substrate division can be done without imposing any stress on an external terminal mounting surface of the matrix substrate.

摘要翻译： 一种半导体器件制造方法，包括以下步骤：提供具有形成在其上的多个器件区域的主表面的矩阵衬底，将多个半导体芯片分别固定到多个器件区域，然后将多个半导体芯片与树脂一起密封以形成块密封 通过切割将每个设备区域的块状密封构件和矩阵基板分开，然后用刷子擦拭每个切割的密封构件部分的表面，然后将通过切割形成的半导体器件分别存储到一个 托盘，并且分别从托盘传送半导体器件。 由于在模块密封部件的表面进行真空夹紧的同时通过切割进行块模塑后的基板分割作业，所以可以在不对矩阵基板的外部端子安装面施加任何应力的情况下进行基板分割。

公开(公告)号：US08614270B2

公开(公告)日：2013-12-24

申请号：US13307289

申请日：2011-11-30

申请人： Hikaru Okubo ,  Nobuki Tanaka ,  Itaru Watanabe

发明人： Hikaru Okubo ,  Nobuki Tanaka ,  Itaru Watanabe

IPC分类号： C08K3/08 ,  C08K3/26 ,  C08F234/02 ,  C08F220/58

CPC分类号： C08F220/58 ,  C08F234/02 ,  C08G73/12 ,  C08K3/08 ,  C08K3/26 ,  C08K5/0025 ,  C08K5/14 ,  C08L79/085 ,  C09J179/08 ,  C09J201/025 ,  H01L23/145 ,  H01L23/3737 ,  H01L24/29 ,  H01L24/83 ,  H01L2224/29111 ,  H01L2224/2919 ,  H01L2224/8385 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01009 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/0102 ,  H01L2924/01024 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01057 ,  H01L2924/01077 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/0132 ,  H01L2924/014 ,  H01L2924/0665 ,  H01L2924/07802 ,  H01L2924/10253 ,  H01L2924/12044 ,  H01L2924/15747 ,  H01L2924/1579 ,  H01L2924/181 ,  H01L2924/30105 ,  H01L2924/00 ,  H01L2924/3512 ,  H01L2924/00015

摘要： A resin composition which is excellent in quick curing and can be used for curing in conventionally used ovens, and a semiconductor device which is excellent in reliability such as solder crack resistance or the like when the resin composition is used as a die attach material for semiconductor. Further preferably, a resin composition which has a sufficient low stress property, good adhesion and excellent bleeding property.A resin composition comprising a filler (A), the compound (B) comprising a structure represented by the formula (1) and a functional group represented by the formula (2) and a thermal radical initiator (C), and substantially not containing a photo polymerization initiator.

摘要翻译： 用于快速固化并可用于常规使用的烘箱中的固化的树脂组合物，以及当树脂组合物用作半导体芯片附着材料时，具有优异的可焊性抗裂性等可靠性的半导体器件 。 进一步优选具有足够的低应力性，良好的粘合性和优异的渗出性的树脂组合物。 一种树脂组合物，其包含填料（A），包含由式（1）表示的结构的化合物（B）和由式（2）表示的官能团和热自由基引发剂（C），并且基本上不含 光聚合引发剂。

公开(公告)号：US20130127026A1

公开(公告)日：2013-05-23

申请号：US13745448

申请日：2013-01-18

申请人： Osamu IKEDA ,  Masahide OKAMOTO

发明人： Osamu IKEDA ,  Masahide OKAMOTO

IPC分类号： H01L23/495 ,  B23K35/02 ,  B32B15/01 ,  B23K20/02

CPC分类号： H01L23/49582 ,  B23K20/02 ,  B23K20/04 ,  B23K35/0238 ,  B32B15/017 ,  H01L24/27 ,  H01L24/29 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L24/743 ,  H01L24/83 ,  H01L2224/291 ,  H01L2224/29111 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48137 ,  H01L2224/48247 ,  H01L2224/73265 ,  H01L2224/83101 ,  H01L2224/83455 ,  H01L2224/83801 ,  H01L2224/83805 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01009 ,  H01L2924/01012 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/0132 ,  H01L2924/01322 ,  H01L2924/0133 ,  H01L2924/014 ,  H01L2924/13055 ,  H01L2924/15747 ,  H01L2924/181 ,  H01L2924/351 ,  Y10T428/12736 ,  Y10T428/31678 ,  H01L2924/01014 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2924/01083 ,  H01L2924/3512 ,  H01L2224/45099 ,  H01L2224/05599

摘要： In a connecting material of the present invention, a Zn series alloy layer is formed on an outermost surface of an Al series alloy layer. In particular, in the connecting material, an Al content of the Al series alloy layer is 99 to 100 wt.% or a Zn content of the Zn series alloy layer is 90 to 100 wt.%. By using this connecting material, the formation of an Al oxide film on the surface of the connecting material at the time of the connection can be suppressed, and preferable wetness that cannot be obtained with the Zn—Al alloy can be obtained. Further, a high connection reliability can be achieved when an Al series alloy layer is left after the connection, since the soft Al thereof functions as a stress buffer material.

摘要翻译： 在本发明的连接材料中，在Al系合金层的最表面上形成Zn系合金层。 特别地，在连接材料中，Al系合金层的Al含量为99〜100重量％，Zn系合金层的Zn含量为90〜100重量％。 通过使用该连接材料，可以抑制在连接时在连接材料的表面上形成Al氧化膜，并且可以获得优选的用Zn-Al合金不能获得的湿度。 此外，由于其软Al作为应力缓冲材料，所以在连接后留下Al系合金层时，可以实现高的连接可靠性。

公开(公告)号：US08097958B2

公开(公告)日：2012-01-17

申请号：US12298464

申请日：2007-04-18

申请人： Susumu Sawada ,  Seiichi Nakatani ,  Seiji Karashima ,  Takashi Kitae

发明人： Susumu Sawada ,  Seiichi Nakatani ,  Seiji Karashima ,  Takashi Kitae

IPC分类号： H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC分类号： H05K3/323 ,  H01L24/11 ,  H01L24/12 ,  H01L24/16 ,  H01L24/29 ,  H01L24/31 ,  H01L24/81 ,  H01L24/83 ,  H01L2224/13099 ,  H01L2224/16225 ,  H01L2224/16501 ,  H01L2224/29101 ,  H01L2224/29111 ,  H01L2224/2929 ,  H01L2224/293 ,  H01L2224/29339 ,  H01L2224/29347 ,  H01L2224/81193 ,  H01L2224/81801 ,  H01L2224/8192 ,  H01L2224/83192 ,  H01L2224/83851 ,  H01L2224/83855 ,  H01L2224/83886 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01009 ,  H01L2924/01011 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01023 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01056 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/0132 ,  H01L2924/014 ,  H01L2924/0665 ,  H01L2924/0781 ,  H01L2924/14 ,  H01L2924/1579 ,  H01L2924/351 ,  H05K3/3436 ,  H05K3/3484 ,  H05K3/361 ,  H05K3/363 ,  H05K2203/083 ,  H05K2203/087 ,  Y02P70/613 ,  H01L2924/00 ,  H01L2924/01083 ,  H01L2224/29311 ,  H01L2924/00014 ,  H01L2924/00015

摘要： A connection structure (package 10) has a first plate body 101 and a second plate body; in the first plate body 101, a wiring pattern having a plurality of connection terminals 102 is formed, and the second plate body has at least two connection terminals (electrode terminals 104) arranged facing the connection terminals of the first plate body 101. The connection terminals of the first and second plate bodies are connection terminals formed as projections on the surfaces of the first and second plate bodies. A conductive substance 108 is accumulated to cover at least a part of each side face of the connection terminals opposed to each other of the first and second plate bodies, and the connection terminals thus opposed are connected to each other via the conductive substance. The package thus formed is ready for a high-pin-count, narrow-pitch configuration of a next-generation semiconductor chip, and exhibits excellent productivity and reliability. The present invention is advantageous for such a package, for a connection structure applicable to the production of the package, and for a method of producing the connection structure.

摘要翻译： 连接结构（封装10）具有第一板体101和第二板体; 在第一板体101中，形成具有多个连接端子102的布线图案，第二板体具有面对第一板体101的连接端子配置的至少两个连接端子（电极端子104）。连接 第一和第二板体的端子是在第一和第二板体的表面上形成为突起的连接端子。 聚集导电物质108以覆盖第一和第二板体彼此相对的连接端子的每个侧面的至少一部分，并且由此相对的连接端子经由导电物质彼此连接。 这样形成的封装准备好用于下一代半导体芯片的高引脚数，窄间距配置，并且表现出优异的生产率和可靠性。 本发明对于这种包装，对于适用于包装的生产的连接结构以及制造连接结构的方法是有利的。

公开(公告)号：US08071425B2

公开(公告)日：2011-12-06

申请号：US12764455

申请日：2010-04-21

申请人： Seiichi Nakatani ,  Takashi Kitae ,  Yoshihisa Yamashita ,  Takashi Ichiryu ,  Seiji Karashima

发明人： Seiichi Nakatani ,  Takashi Kitae ,  Yoshihisa Yamashita ,  Takashi Ichiryu ,  Seiji Karashima

IPC分类号： H01L21/52

CPC分类号： H01L24/81 ,  H01L21/563 ,  H01L24/16 ,  H01L24/29 ,  H01L24/32 ,  H01L24/75 ,  H01L24/83 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16225 ,  H01L2224/29111 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2224/75 ,  H01L2224/75251 ,  H01L2224/83007 ,  H01L2224/83097 ,  H01L2224/83192 ,  H01L2224/83815 ,  H01L2224/83874 ,  H01L2224/8388 ,  H01L2224/83888 ,  H01L2224/9201 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01009 ,  H01L2924/01011 ,  H01L2924/01013 ,  H01L2924/01027 ,  H01L2924/01033 ,  H01L2924/0105 ,  H01L2924/01056 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/0132 ,  H01L2924/014 ,  H01L2924/0665 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/3025 ,  H01L2924/00 ,  H01L2924/0695 ,  H01L2224/05599

摘要： The flip chip mounted body of the present invention includes: a circuit board (213) having a plurality of connection terminals (211); a semiconductor chip (206) having a plurality of electrode terminals (207) that are disposed opposing the connection terminals (211); and a porous sheet (205) having a box shape that is provided on an opposite side of a formation surface of the electrode terminal (207) of the semiconductor chip (206), is folded on an outer periphery of the semiconductor chip (206) on the formation surface side of the electrode terminal (207) and is in contact with the circuit board (213), wherein the connection terminal (211) of the circuit board (213) and the electrode terminal (207) of the semiconductor chip (206) are connected electrically via a solder layer (215), and the circuit board (213) and the semiconductor chip (206) are fixed by a resin (217). Thereby, the flip chip mounted body with excellent productivity and reliability that can mount the semiconductor chip on the circuit board, and a method and an apparatus for mounting the flip chip mounted body are provided.

摘要翻译： 本发明的倒装芯片安装体包括：具有多个连接端子（211​​）的电路板（213）; 具有与所述连接端子相对设置的多个电极端子（207）的半导体芯片（206）。 在所述半导体芯片（206）的外周折叠具有设置在所述半导体芯片（206）的所述电极端子（207）的形成面的相反侧的盒状的多孔片（205） 在电极端子（207）的形成面侧与电路基板（213）接触，电路基板（213）的连接端子（211​​）和半导体芯片的电极端子（207） 206）通过焊料层（215）电连接，并且电路板（213）和半导体芯片（206）由树脂（217）固定。 因此，提供了将半导体芯片安装在电路板上的优异的生产率和可靠性的倒装芯片安装体以及安装倒装芯片安装体的方法和装置。

公开(公告)号：US08039307B2

公开(公告)日：2011-10-18

申请号：US12728615

申请日：2010-03-22

申请人： Toshiyuki Kojima ,  Seiichi Nakatani ,  Yoshihisa Yamashita ,  Takashi Kitae ,  Shingo Komatsu

发明人： Toshiyuki Kojima ,  Seiichi Nakatani ,  Yoshihisa Yamashita ,  Takashi Kitae ,  Shingo Komatsu

IPC分类号： H01L23/498

CPC分类号： H01L24/81 ,  H01L21/6835 ,  H01L23/4952 ,  H01L23/49524 ,  H01L23/5389 ,  H01L24/16 ,  H01L24/17 ,  H01L24/24 ,  H01L24/25 ,  H01L24/45 ,  H01L24/48 ,  H01L24/82 ,  H01L24/83 ,  H01L2224/0554 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16058 ,  H01L2224/16059 ,  H01L2224/16105 ,  H01L2224/16106 ,  H01L2224/16238 ,  H01L2224/17051 ,  H01L2224/171 ,  H01L2224/24011 ,  H01L2224/24225 ,  H01L2224/24226 ,  H01L2224/24227 ,  H01L2224/32225 ,  H01L2224/45015 ,  H01L2224/45144 ,  H01L2224/48247 ,  H01L2224/73204 ,  H01L2224/82001 ,  H01L2224/83385 ,  H01L2224/83886 ,  H01L2224/83888 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01009 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/15153 ,  H01L2924/15165 ,  H01L2924/15311 ,  H01L2924/15788 ,  H01L2924/181 ,  H01L2924/19043 ,  H01L2924/3025 ,  H01L2224/16225 ,  H01L2924/00 ,  H01L2924/20752 ,  H01L2924/00015 ,  H01L2224/81805 ,  H01L2924/00012 ,  H01L2224/05599 ,  H01L2224/0555 ,  H01L2224/0556

摘要： A mounted body (100) of the present invention includes: a semiconductor element (10) having a surface (10a) on which element electrodes (12) are formed and a rear surface (10b) opposing the surface (10a); and a mounting board (30) on which wiring patterns (35) each having an electrode terminal (32) are formed. The rear surface (10b) of the semiconductor element (10) is in contact with the mounting board (30), and the element electrodes (12) of the semiconductor element (10) are connected electrically to the electrode terminals (32) of the wiring pattern (35) formed on the mounting board (30) via solder connectors (20) formed of solder particles assembled into a bridge shape. With this configuration, fine pitch connection between the element electrodes of the semiconductor element and the electrode terminals of the mounting board becomes possible.

摘要翻译： 本发明的安装体（100）包括：具有形成元件电极（12）的表面（10a）和与表面（10a）相对的后表面（10b）的半导体元件（10）。 以及安装板（30），在其上形成有各自具有电极端子（32）的布线图案（35）。 半导体元件（10）的后表面（10b）与安装板（30）接触，并且半导体元件（10）的元件电极（12）与电极端子（32）电连接 通过由组装成桥形的焊料颗粒形成的焊料连接器（20）在安装板（30）上形成的布线图案（35）。 利用这种结构，半导体元件的元件电极和安装板的电极端子之间的细间距连接成为可能。