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公开(公告)号：US11763875B2
公开(公告)日：2023-09-19
申请号：US17331340
申请日：2021-05-26
IPC分类号： G11C8/10 , G11C11/408 , G11C11/4096 , G11C11/4094
CPC分类号： G11C11/4087 , G11C11/4085 , G11C11/4094 , G11C11/4096
摘要： A memory device is disclosed. The memory device includes a plurality of memory cells arranged in a plurality of rows and a plurality of columns; a plurality of word lines, each of the word lines coupled to a corresponding row of the memory cells; a plurality of bit lines, each of the bit lines coupled to a corresponding column of the memory cells; and a plurality of second word lines, each of the second word lines coupled to a corresponding column of the memory cells.
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公开(公告)号：US20230282296A1
公开(公告)日：2023-09-07
申请号：US18317214
申请日：2023-05-15
发明人： Perng-Fei Yuh
摘要： In some aspects of the present disclosure, a memory array includes: a plurality of memory cells; and a plurality of logic gates, each of the plurality of logic gates having a first input, a second input, and an output gating a corresponding one of the plurality of memory cells, wherein the first input of each of the plurality of logic gates of a first subset is coupled to a first bit select line.
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公开(公告)号：US11545218B2
公开(公告)日：2023-01-03
申请号：US17094307
申请日：2020-11-10
发明人： Perng-Fei Yuh , Jui-Che Tsai , Hiroki Noguchi , Yih Wang
IPC分类号： G11C11/419 , G11C14/00 , G11C11/412 , G11C11/16 , G11C11/418
摘要： A memory device has a plurality of bit cells, each of which includes an SRAM cell having a storage node selectively connectable to a first bit line in response to a control signal received on a first word line. Each bit cell further includes an MRAM cell selectively connectable to the storage node of the SRAM cell in response to a control signal received on a second word line.
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公开(公告)号：US20220336294A1
公开(公告)日：2022-10-20
申请号：US17397989
申请日：2021-08-10
发明人： Chansyun Yang , Chan-Lon Yang , Keh-Jeng Chang , Perng-Fei Yuh
IPC分类号： H01L21/66 , G03F7/20 , H01L21/67 , H01L21/027
摘要： An apparatus includes a beam conditioning assembly configured to output one or more wavelengths to a substrate being processed and receive one or more reflected wavelengths from the substrate, and a machine learning device configured to process the one or more reflected wavelengths to predict a process variable and compare the predicted process variable with a measured process variable to obtain a comparison result.
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公开(公告)号：US20220328116A1
公开(公告)日：2022-10-13
申请号：US17484730
申请日：2021-09-24
发明人： Perng-Fei Yuh , Tung-Cheng Chang , Gu-Huan Li , Chia-En Huang , Jimmy Lee , Yih Wang
IPC分类号： G11C17/16 , H01L27/112 , G11C17/18
摘要： A memory device and a method of operating a memory device are disclosed. In one aspect, the memory device includes a plurality of non-volatile memory cells, each of the plurality of non-volatile memory cells is operatively coupled to a word line, a gate control line, and a bit line. Each of the plurality of non-volatile memory cells comprises a first transistor, a second transistor, a first diode-connected transistor, and a capacitor. The first transistor, second transistor, first diode-connected transistor are coupled in series, with the capacitor having a first terminal connected to a common node between the first diode-connected transistor and the second transistor.
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公开(公告)号：US11450370B2
公开(公告)日：2022-09-20
申请号：US17229194
申请日：2021-04-13
发明人： Perng-Fei Yuh
IPC分类号： G11C11/22 , G11C11/56 , H01L27/11585
摘要： A memory device includes a plurality of memory cells. Each memory cell includes a multi-gate FeFET that has a first source/drain terminal, a second source/drain terminal, and a gate with a plurality of ferroelectric layers configured such that each of the ferroelectric layers has a respective unique switching E-field.
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公开(公告)号：US20210201998A1
公开(公告)日：2021-07-01
申请号：US17094307
申请日：2020-11-10
发明人： Perng-Fei Yuh , Jui-Che Tsai , Hiroki Noguchi , Yih Wang
IPC分类号： G11C14/00 , G11C11/412 , G11C11/419 , G11C11/418 , G11C11/16
摘要： A memory device has a plurality of bit cells, each of which includes an SRAM cell having a storage node selectively connectable to a first bit line in response to a control signal received on a first word line. Each bit cell further includes an MRAM cell selectively connectable to the storage node of the SRAM cell in response to a control signal received on a second word line.
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公开(公告)号：US20240290836A1
公开(公告)日：2024-08-29
申请号：US18650905
申请日：2024-04-30
IPC分类号： H01L29/06 , H01L21/8234 , H01L29/66 , H01L29/78
CPC分类号： H01L29/0673 , H01L21/823418 , H01L21/823431 , H01L29/66795 , H01L29/7851
摘要： A semiconductor device with different configurations of gate structures and a method of fabricating the semiconductor device are disclosed. The semiconductor device includes a stack of nanostructured channel regions disposed on a fin structure, a first gate structure disposed within the stack of nanostructured channel regions, a second gate structure surrounds the first gate structure about a first axis and surrounds the nanostructured channel regions about a second axis different from the first axis, and first and second contact structures disposed on the first and second gate structures, respectively.
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公开(公告)号：US20240249785A1
公开(公告)日：2024-07-25
申请号：US18627427
申请日：2024-04-04
发明人： Perng-Fei Yuh
摘要： In some aspects of the present disclosure, a memory array includes: a plurality of memory cells; and a plurality of logic gates, each of the plurality of logic gates having a first input, a second input, and an output gating a corresponding one of the plurality of memory cells, wherein the first input of each of the plurality of logic gates of a first subset is coupled to a first bit select line.
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公开(公告)号：US11955190B2
公开(公告)日：2024-04-09
申请号：US18317214
申请日：2023-05-15
发明人： Perng-Fei Yuh
摘要： In some aspects of the present disclosure, a memory array includes: a plurality of memory cells; and a plurality of logic gates, each of the plurality of logic gates having a first input, a second input, and an output gating a corresponding one of the plurality of memory cells, wherein the first input of each of the plurality of logic gates of a first subset is coupled to a first bit select line.
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