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    Memory device and operating method of the same
    3.
    发明授权
    Memory device and operating method of the same 有权

    公开(公告)号：US12002528B2

    公开(公告)日：2024-06-04

    申请号：US18345530

    申请日：2023-06-30

    申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

    发明人： Gu-Huan Li ,  Tung-Cheng Chang ,  Perng-Fei Yuh ,  Chia-En Huang ,  Chun-Ying Lee ,  Yih Wang

    IPC分类号： G11C17/18 ,  G11C17/16 ,  H10B20/20

    CPC分类号： G11C17/18 ,  G11C17/16 ,  H10B20/20

    摘要： A memory device is provided, including a first bit cell including a first memory cell coupled to a first word line and a second bit cell including a second memory cell coupled to a second word line. The first and second memory cells are coupled to a first control line and further coupled to a first bit line through first and second nodes. The second bit cell further includes a first protection array coupled to the second memory cell at the second node coupled to the first bit line and further coupled to a third word line. When the first and second bit cells operate in different operational types, the first protection array is configured to generate an adjust voltage to the second node according to a voltage level of the third word line while the first bit cell is programmed.

    Memory circuit and method of operating same
    4.
    发明授权
    Memory circuit and method of operating same 有权

    公开(公告)号：US11862264B2

    公开(公告)日：2024-01-02

    申请号：US18155925

    申请日：2023-01-18

    申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

    发明人： Chun-Hao Chang ,  Gu-Huan Li ,  Shao-Yu Chou

    IPC分类号： G11C17/18 ,  G11C17/16

    CPC分类号： G11C17/18 ,  G11C17/16

    摘要： A memory circuit includes a sense amplifier coupled to a non-volatile memory cell, and a detection circuit coupled to the sense amplifier and the non-volatile memory cell. The sense amplifier includes a comparator. The comparator includes a first input terminal coupled to the non-volatile memory cell by a first node, and configured to receive a first voltage, a second input terminal configured to receive a second voltage, and a first output terminal configured to output a first output signal. The detection circuit is configured to latch the first output signal and disrupt a current path between the non-volatile memory cell and the sense amplifier. The detection circuit includes a first inverter. A first input terminal of the first inverter is configured to receive the first output signal. A first output terminal of the first inverter is configured to generate an inverted first output signal.

    SEMICONDUCTOR MEMORY DEVICES WITH DIFFERENT WORD LINES
    7.
    发明申请
    SEMICONDUCTOR MEMORY DEVICES WITH DIFFERENT WORD LINES 有权

    公开(公告)号：US20220351774A1

    公开(公告)日：2022-11-03

    申请号：US17482073

    申请日：2021-09-22

    申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

    发明人： Meng-Sheng Chang ,  Chia-En Huang ,  Gu-Huan Li

    IPC分类号： G11C13/00

    摘要： A memory device includes a bit line (BL); a source line (SL); and a plurality of non-volatile memory cells operatively coupled between the BL and SL, respectively. Each of the plurality of non-volatile memory cells includes a resistor with a variable resistance, a first transistor, and a second transistor that are coupled to each other in series. In response to a first one of the non-volatile memory cell not being read and a second one of the non-volatile memory cell being read, a voltage level at a first node connected between the first and second transistors of the first non-volatile memory cell is greater than zero.

    Memory controller, memory device and method of operating
    8.
    发明授权
    Memory controller, memory device and method of operating 有权

    公开(公告)号：US10141063B2

    公开(公告)日：2018-11-27

    申请号：US14075097

    申请日：2013-11-08

    申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

    发明人： Yue-Der Chih ,  Cheng-Hsiung Kuo ,  Gu-Huan Li

    IPC分类号： G11C16/34 ,  G11C16/14 ,  G11C16/24

    摘要： A memory controller has a bit line driver configured to supply a selected bit line voltage to a selected bit line and an unselected bit line voltage to an unselected bit line. The selected bit line is coupled to a selected memory cell, and the unselected bit line is coupled to an unselected memory cell. The memory controller further has a word line driver configured to supply a selected word line voltage to a selected word line and an unselected word line voltage to an unselected word line. The selected word line is coupled to the selected memory cell, and the unselected word line is coupled to the unselected memory cell. The unselected bit line voltage is equal to or higher than a difference between the unselected word line voltage and a threshold voltage of the unselected memory cell.

    Multiple power domain electronic device and related method
    9.
    发明授权
    Multiple power domain electronic device and related method 有权
    多功率域电子设备及相关方法

    公开(公告)号：US08928372B2

    公开(公告)日：2015-01-06

    申请号：US13791155

    申请日：2013-03-08

    申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

    发明人： Jerry Chen ,  Hsu-Shun Chen ,  Gu-Huan Li ,  Cheng-Hsiung Kuo ,  Yue-Der Chih

    IPC分类号： H03L7/00 ,  H03K17/22

    CPC分类号： H03K17/223 ,  G06F1/24 ,  G06F1/26

    摘要： An electronic device includes a first circuit, a second circuit, and a power on control (POC) circuit. The POC circuit includes an enable terminal electrically connected to a first output of the first circuit, a first input terminal electrically connected to a first voltage supply, a second input terminal electrically connected to a second voltage supply, and an output terminal. The second circuit includes a biasing-sensitive circuit, and a logic circuit including a first input terminal electrically connected to a second output of the first circuit, a second input terminal electrically connected to the output of the POC circuit, and an output terminal electrically connected to an enable terminal of the biasing-sensitive circuit.

    摘要翻译： 电子设备包括第一电路，第二电路和上电控制（POC）电路。 POC电路包括电连接到第一电路的第一输出的使能端子，电连接到第一电压源的第一输入端子，电连接到第二电压源的第二输入端子和输出端子。 第二电路包括偏置敏感电路，以及包括电连接到第一电路的第二输出的第一输入端的逻辑电路，电连接到POC电路的输出的第二输入端和电连接的输出端 到偏置敏感电路的使能端子。