公开(公告)号：US08642407B2

公开(公告)日：2014-02-04

申请号：US12939506

申请日：2010-11-04

申请人： Tak H. Ning ,  Philip J. Oldiges

发明人： Tak H. Ning ,  Philip J. Oldiges

IPC分类号： H01L21/00

CPC分类号： H01L21/84 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823878

摘要： A semiconductor-on-insulator (SOI) substrate complementary metal oxide semiconductor (CMOS) device and fabrication methods include a p-type field effect transistor (PFET) and an n-type field effect transistor (NFET). Each of the PFET and the NFET include a transistor body of a first type of material and source and drain regions. The source and drain regions have a second type of material such that an injection charge into the source and drain region is greater than a parasitic charge into the transistor body to decrease parasitic bipolar current gain, increase critical charge (Qcrit) and reduce sensitivity to soft errors.

摘要翻译： 绝缘体上半导体（SOI）衬底互补金属氧化物半导体（CMOS）器件和制造方法包括p型场效应晶体管（PFET）和n型场效应晶体管（NFET）。 PFET和NFET中的每一个包括第一类材料和源极和漏极区的晶体管体。 源极和漏极区域具有第二类型的材料，使得源极和漏极区域中的注入电荷大于晶体管本体中的寄生电荷以降低寄生双极性电流增益，增加临界电荷（Qcrit）并降低对软件的灵敏度 错误。

公开(公告)号：US08354858B2

公开(公告)日：2013-01-15

申请号：US12987106

申请日：2011-01-08

申请人： Ethan H. Cannon ,  AJ KleinOsowski ,  K. Paul Muller ,  Tak H. Ning ,  Philip J. Oldiges ,  Leon J. Sigal ,  James D. Warnock ,  Dieter Wendel

发明人： Ethan H. Cannon ,  AJ KleinOsowski ,  K. Paul Muller ,  Tak H. Ning ,  Philip J. Oldiges ,  Leon J. Sigal ,  James D. Warnock ,  Dieter Wendel

IPC分类号： G01R31/26

CPC分类号： H03K3/356156 ,  H03K3/0375

摘要： A method of determining one or more transistors within a particular circuit to be respectively replaced with a hardened transistor includes: identifying, as not requiring hardening, one or more transistors; identifying, as candidates for hardening, each transistor in the circuit not previously identified as not requiring hardening; and employing the hardened transistor in place of a transistor identified as a candidate for hardening. The circuit is a latch and the transistor is an SOI CMOS FET. The transistor is also an SOI transistor. The series transistor includes first and second series-connected transistors having a shared source/drain region whereby a drain of the first series-connected transistor is merged with a source of the second series-connected transistor.

摘要翻译： 确定特定电路内分别被硬化晶体管替代的一个或多个晶体管的方法包括：鉴定为不需要硬化一个或多个晶体管; 识别作为硬化的候选者，电路中的每个晶体管先前未被识别为不需要硬化; 并且使用硬化晶体管代替被鉴定为硬化候选的晶体管。 该电路是锁存器，晶体管是SOI CMOS FET。 晶体管也是SOI晶体管。 串联晶体管包括具有共享源极/漏极区域的第一和第二串联连接的晶体管，由此第一串联晶体管的漏极与第二串联晶体管的源极合并。

公开(公告)号：US07888959B2

公开(公告)日：2011-02-15

申请号：US11857596

申请日：2007-09-19

申请人： Ethan H. Cannon ,  AJ KleinOsowski ,  K. Paul Muller ,  Tak H. Ning ,  Philip J. Oldiges ,  Leon J. Sigal ,  James D. Warnock ,  Dieter Wendel

发明人： Ethan H. Cannon ,  AJ KleinOsowski ,  K. Paul Muller ,  Tak H. Ning ,  Philip J. Oldiges ,  Leon J. Sigal ,  James D. Warnock ,  Dieter Wendel

IPC分类号： G01R31/26

CPC分类号： H03K3/356156 ,  H03K3/0375

摘要： A method of determining one or more transistors within a particular circuit to be respectively replaced with a hardened transistor includes: identifying, as not requiring hardening, one or more transistors; identifying, as candidates for hardening, each transistor in the circuit not previously identified as not requiring hardening; and employing the hardened transistor in place of a transistor identified as a candidate for hardening. The circuit is a latch and the transistor is an SOI CMOS FET. The transistor is also an SOI transistor. The series transistor includes first and second series-connected transistors having a shared source/drain region whereby a drain of the first series-connected transistor is merged with a source of the second series-connected transistor.

摘要翻译： 确定特定电路内分别被硬化晶体管替代的一个或多个晶体管的方法包括：鉴定为不需要硬化一个或多个晶体管; 识别作为硬化的候选者，电路中的每个晶体管先前未被识别为不需要硬化; 并且使用硬化晶体管代替被鉴定为硬化候选的晶体管。 该电路是锁存器，晶体管是SOI CMOS FET。 晶体管也是SOI晶体管。 串联晶体管包括具有共享源极/漏极区域的第一和第二串联连接的晶体管，由此第一串联晶体管的漏极与第二串联晶体管的源极合并。

公开(公告)号：US20090072313A1

公开(公告)日：2009-03-19

申请号：US11857569

申请日：2007-09-19

申请人： Jin Cai ,  Wilfried E. Haensch ,  Tak H. Ning ,  Philip J. Oldiges ,  Ghavam G. Shahidi

发明人： Jin Cai ,  Wilfried E. Haensch ,  Tak H. Ning ,  Philip J. Oldiges ,  Ghavam G. Shahidi

IPC分类号： H01L27/12

CPC分类号： H01L27/1203 ,  H01L21/823425 ,  H01L21/84 ,  H01L27/07 ,  H01L29/785 ,  H01L29/78612

摘要： A series transistor device includes a series source, a series drain, a first constituent transistor, and a second constituent transistor. The first constituent transistor has a first source and a first drain, and the second constituent transistor has a second source and a second drain. All of the constituent transistors have a same conductivity type. The series source is the first source, and the series drain is the second drain. A drain of one of the constituent transistors is merged with a source of another of the constituent transistors.

摘要翻译： 串联晶体管器件包括串联源极，串联漏极，第一构成晶体管和第二构成晶体管。 第一构成晶体管具有第一源极和第一漏极，并且第二构成晶体管具有第二源极和第二漏极。 所有构成晶体管都具有相同的导电类型。 串联源是第一个源，串联漏极是第二个漏极。 一个构成晶体管的漏极与另一个构成晶体管的源极合并。

公开(公告)号：US08890256B2

公开(公告)日：2014-11-18

申请号：US12408205

申请日：2009-03-20

申请人： Mark C. Hakey ,  Tak H. Ning ,  Philip J. Oldiges ,  Henry H. K. Tang

发明人： Mark C. Hakey ,  Tak H. Ning ,  Philip J. Oldiges ,  Henry H. K. Tang

IPC分类号： H01L29/76 ,  H01L29/94 ,  H01L21/8238

CPC分类号： H01L21/84 ,  H01L21/823418 ,  H01L21/823481 ,  H01L21/823814 ,  H01L21/823878 ,  H01L27/12 ,  H01L29/78

摘要： The invention relates to a design structure, and more particularly, to a design structure for a heavy ion tolerant device, method of manufacturing the same and a structure thereof. The structure includes a first device having a diffusion comprising a drain region and source region and a second device having a diffusion comprising a drain region and source region. The first and second device are aligned in an end-to-end layout along a width of the diffusion of the first device and the second device. A first isolation region separating the diffusion of the first device and the second device.

摘要翻译： 本发明涉及一种设计结构，更具体地，涉及一种用于重离子容错装置的设计结构，其制造方法及其结构。 该结构包括具有包括漏极区域和源极区域的扩散的第一器件和具有包括漏极区域和源极区域的扩散部分的第二器件。 第一和第二装置沿着第一装置和第二装置的扩散的宽度在端对端布局中对准。 分离第一装置和第二装置的扩散的第一隔离区。

公开(公告)号：US20110102042A1

公开(公告)日：2011-05-05

申请号：US12987106

申请日：2011-01-08

申请人： Ethan H. Cannon ,  AJ KleinOsowski ,  K. Paul Muller ,  Tak H. Ning ,  Philip J. Oldiges ,  Leon J. Sigal ,  James D. Warnock ,  Dieter Wendel

发明人： Ethan H. Cannon ,  AJ KleinOsowski ,  K. Paul Muller ,  Tak H. Ning ,  Philip J. Oldiges ,  Leon J. Sigal ,  James D. Warnock ,  Dieter Wendel

IPC分类号： H03K3/00

CPC分类号： H03K3/356156 ,  H03K3/0375

摘要： A method of determining one or more transistors within a particular circuit to be respectively replaced with a hardened transistor includes: identifying, as not requiring hardening, one or more transistors; identifying, as candidates for hardening, each transistor in the circuit not previously identified as not requiring hardening; and employing the hardened transistor in place of a transistor identified as a candidate for hardening. The circuit is a latch and the transistor is an SOI CMOS FET. The transistor is also an SOI transistor. The series transistor includes first and second series-connected transistors having a shared source/drain region whereby a drain of the first series-connected transistor is merged with a source of the second series-connected transistor.

摘要翻译： 确定特定电路内分别被硬化晶体管替代的一个或多个晶体管的方法包括：鉴定为不需要硬化一个或多个晶体管; 识别作为硬化的候选者，电路中的每个晶体管先前未被识别为不需要硬化; 并且使用硬化晶体管代替被鉴定为硬化候选的晶体管。 该电路是锁存器，晶体管是SOI CMOS FET。 晶体管也是SOI晶体管。 串联晶体管包括具有共享源极/漏极区域的第一和第二串联连接的晶体管，由此第一串联晶体管的漏极与第二串联晶体管的源极合并。

公开(公告)号：US20100237389A1

公开(公告)日：2010-09-23

申请号：US12408205

申请日：2009-03-20

申请人： Mark C. HAKEY ,  Tak H. Ning ,  Philip J. Oldiges ,  Henry H.K. Tang

发明人： Mark C. HAKEY ,  Tak H. Ning ,  Philip J. Oldiges ,  Henry H.K. Tang

IPC分类号： H01L29/772 ,  H01L21/8232 ,  G06F17/50

CPC分类号： H01L21/84 ,  H01L21/823418 ,  H01L21/823481 ,  H01L21/823814 ,  H01L21/823878 ,  H01L27/12 ,  H01L29/78

摘要： The invention relates to a design structure, and more particularly, to a design structure for a heavy ion tolerant device, method of manufacturing the same and a structure thereof. The structure includes a first device having a diffusion comprising a drain region and source region and a second device having a diffusion comprising a drain region and source region. The first and second device are aligned in an end-to-end layout along a width of the diffusion of the first device and the second device. A first isolation region separating the diffusion of the first device and the second device.

摘要翻译： 本发明涉及一种设计结构，更具体地，涉及一种用于重离子容错装置的设计结构，其制造方法及其结构。 该结构包括具有包括漏极区域和源极区域的扩散的第一器件和具有包括漏极区域和源极区域的扩散部分的第二器件。 第一和第二装置沿着第一装置和第二装置的扩散的宽度在端对端布局中对准。 分离第一装置和第二装置的扩散的第一隔离区。

公开(公告)号：US20090134925A1

公开(公告)日：2009-05-28

申请号：US11857596

申请日：2007-09-19

申请人： Ethan H. Cannon ,  AJ KleinOsowski ,  K. Paul Muller ,  Tak H. Ning ,  Philip J. Oldiges ,  Leon J. Sigal ,  James D. Warnock ,  Dieter Wendel

发明人： Ethan H. Cannon ,  AJ KleinOsowski ,  K. Paul Muller ,  Tak H. Ning ,  Philip J. Oldiges ,  Leon J. Sigal ,  James D. Warnock ,  Dieter Wendel

IPC分类号： H03K3/356 ,  H03K3/00

CPC分类号： H03K3/356156 ,  H03K3/0375

摘要： A method of determining one or more transistors within a particular circuit to be respectively replaced with a hardened transistor includes: identifying, as not requiring hardening, one or more transistors; identifying, as candidates for hardening, each transistor in the circuit not previously identified as not requiring hardening; and employing the hardened transistor in place of a transistor identified as a candidate for hardening. The circuit is a latch and the transistor is an SOI CMOS FET. The transistor is also an SOI transistor. The series transistor includes first and second series-connected transistors having a shared source/drain region whereby a drain of the first series-connected transistor is merged with a source of the second series-connected transistor.

摘要翻译： 确定特定电路内分别被硬化晶体管替代的一个或多个晶体管的方法包括：鉴定为不需要硬化一个或多个晶体管; 识别作为硬化的候选者，电路中的每个晶体管先前未被识别为不需要硬化; 并且使用硬化晶体管代替被鉴定为硬化候选的晶体管。 该电路是锁存器，晶体管是SOI CMOS FET。 晶体管也是SOI晶体管。 串联晶体管包括具有共享源极/漏极区域的第一和第二串联连接的晶体管，由此第一串联晶体管的漏极与第二串联晶体管的源极合并。

公开(公告)号：US08859302B2

公开(公告)日：2014-10-14

申请号：US13036243

申请日：2011-02-28

申请人： Ali Khakifirooz ,  Jin Cai ,  Kangguo Cheng ,  Robert H. Dennard ,  Tak H. Ning

发明人： Ali Khakifirooz ,  Jin Cai ,  Kangguo Cheng ,  Robert H. Dennard ,  Tak H. Ning

IPC分类号： H01L21/66 ,  G11C11/412 ,  H01L27/11 ,  H01L27/12 ,  H01L21/84 ,  H01L27/115 ,  H01L29/66

CPC分类号： G11C11/418 ,  G11C11/412 ,  G11C11/419 ,  G11C29/50004 ,  G11C2029/5004 ,  G11C2029/5006 ,  H01L21/84 ,  H01L27/11 ,  H01L27/1104 ,  H01L27/1108 ,  H01L27/11568 ,  H01L27/1203 ,  H01L29/0603 ,  H01L29/66833 ,  H01L29/786 ,  H01L29/792

摘要： A semiconductor device including a charge storage element present in a buried dielectric layer of the substrate on which the semiconductor device is formed. Charge injection may be used to introduce charge to the charge storage element of the buried dielectric layer that is present within the substrate. The charge that is injected to the charge storage element may be used to adjust the threshold voltage (Vt) of each of the semiconductor devices within an array of semiconductor devices that are present on the substrate.

摘要翻译： 一种半导体器件，包括存在于其上形成有半导体器件的衬底的埋置介质层中的电荷存储元件。 可以使用电荷注入来将电荷引入存在于衬底内的掩埋介电层的电荷存储元件。 注入电荷存储元件的电荷可用于调整存在于基板上的半导体器件阵列内的每个半导体器件的阈值电压（Vt）。

公开(公告)号：US08558282B1

公开(公告)日：2013-10-15

申请号：US13607672

申请日：2012-09-08

申请人： Jin Cai ,  Kevin K. Chan ,  Christopher P. D'Emic ,  Bahman Hekmatshoartabari ,  Tak H. Ning ,  Dae-Gyu Park

发明人： Jin Cai ,  Kevin K. Chan ,  Christopher P. D'Emic ,  Bahman Hekmatshoartabari ,  Tak H. Ning ,  Dae-Gyu Park

IPC分类号： H01L21/331

CPC分类号： H01L29/6625 ,  H01L29/161 ,  H01L29/735

摘要： A germanium lateral bipolar junction transistor (BJT) is formed employing a germanium-on-insulator (GOI) substrate. A silicon passivation layer is deposited on the top surface of a germanium layer in the GOI substrate. Shallow trench isolation structures, an extrinsic base region structure, and a base spacer are subsequently formed. A germanium emitter region, a germanium base region, and a germanium collector region are formed within the germanium layer by ion implantation. A silicon emitter region, a silicon base region, and a silicon collector region are formed in the silicon passivation layer. After optional formation of an emitter contact region and a collector contact region, metal semiconductor alloy regions can be formed. A wide gap contact for minority carriers is provided between the silicon base region and the germanium base region and between the silicon emitter region and the germanium emitter region.