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    Implantation of gate regions in semiconductor device fabrication
    8.
    发明授权
    Implantation of gate regions in semiconductor device fabrication 失效
    在半导体器件制造中植入栅极区域

    公开(公告)号：US07557023B2

    公开(公告)日：2009-07-07

    申请号：US11532189

    申请日：2006-09-15

    Applicant: Toshiharu Furukawa ,  Mark C. Hakey ,  Steven J. Holmes ,  David V. Horak ,  Charles W. Koburger, III

    Inventor： Toshiharu Furukawa ,  Mark C. Hakey ,  Steven J. Holmes ,  David V. Horak ,  Charles W. Koburger, III

    IPC: H01L21/425

    CPC classification number: H01L29/66545 ,  H01L21/0273 ,  H01L21/266 ,  H01L21/28035 ,  H01L29/1083 ,  H01L29/6653 ,  H01L29/6659

    Abstract: A semiconductor fabrication method. The method includes providing a semiconductor structure which includes (i) a semiconductor layer, (ii) a gate dielectric layer on the semiconductor layer, and (iii) a gate electrode region on the gate dielectric layer. The gate dielectric layer is sandwiched between and electrically insulates the semiconductor layer and the gate electrode region. The semiconductor layer and the gate dielectric layer share a common interfacing surface which defines a reference direction perpendicular to the common interfacing surface and pointing from the semiconductor layer to the gate dielectric layer. Next, a resist layer is formed on the gate dielectric layer and the gate electrode region. Next, a cap portion of the resist layer directly above the gate electrode region in the reference direction is removed without removing any portion of the resist layer not directly above the gate electrode region in the reference direction.

    Abstract translation: 半导体制造方法。 该方法包括提供半导体结构，其包括（i）半导体层，（ii）半导体层上的栅极电介质层，以及（iii）栅极电介质层上的栅电极区。 栅极电介质层被夹在半导体层和栅极电极区域之间并使其电绝缘。 半导体层和栅极介电层共享公共接口表面，其界定垂直于公共接口表面的参考方向并且从半导体层指向栅极介电层。 接下来，在栅极电介质层和栅极电极区域上形成抗蚀剂层。 接下来，去除在参考方向上正好在栅极区域上方的抗蚀剂层的盖部分，而不去除在参考方向上不在栅电极区域正上方的任何部分的抗蚀剂层。

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