公开(公告)号：US08241999B2

公开(公告)日：2012-08-14

申请号：US12706056

申请日：2010-02-16

申请人： Takafumi Ikeda ,  Takahito Nakazawa ,  Hideaki Maekawa ,  Yuuichi Tatsumi ,  Toshifumi Minami

发明人： Takafumi Ikeda ,  Takahito Nakazawa ,  Hideaki Maekawa ,  Yuuichi Tatsumi ,  Toshifumi Minami

IPC分类号： H01L23/544 ,  H01L21/301

CPC分类号： H01L23/585 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device has a circuit element region formed on a semiconductor substrate, and a protective pattern formed so as to surround the circuit element region. The protective pattern comprises a first element separation region formed on the semiconductor substrate, a second element separation region formed on the semiconductor substrate and having a width smaller than that of the first element separation region, a first element region formed between the first element separation region and the second element separation region, a first gate layer formed on the first element separation region, a wiring layer formed on the first gate layer, a passivation layer formed above the wiring layer, a second element region, an insulation film formed on the second element region, and a second gate layer formed on the insulation film, the first element separation region, the first element region, the second element separation region and the second element region being located in this order from the nearer side of the circuit element region.

摘要翻译： 半导体器件具有形成在半导体衬底上的电路元件区域和形成为围绕电路元件区域的保护图案。 保护图案包括形成在半导体衬底上的第一元件分离区域，形成在半导体衬底上的第二元件分离区域，其宽度小于第一元件分离区域的宽度;第一元素区域，形成在第一元素分离区域 和第二元件分离区域，形成在第一元件分离区域上的第一栅极层，形成在第一栅极层上的布线层，形成在布线层上方的钝化层，第二元素区域，形成在第二栅极层上的绝缘膜 元件区域和形成在绝缘膜上的第二栅极层，第一元件分离区域，第一元件区域，第二元件分离区域和第二元件区域从电路元件区域的更靠近的方向定位。

公开(公告)号：US20100237438A1

公开(公告)日：2010-09-23

申请号：US12706056

申请日：2010-02-16

申请人： Takafumi IKEDA ,  Takahito Nakazawa ,  Hideaki Maekawa ,  Yuuichi Tatsumi ,  Toshifumi Minami

发明人： Takafumi IKEDA ,  Takahito Nakazawa ,  Hideaki Maekawa ,  Yuuichi Tatsumi ,  Toshifumi Minami

IPC分类号： H01L29/06

CPC分类号： H01L23/585 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device has a circuit element region formed on a semiconductor substrate, and a protective pattern formed so as to surround the circuit element region. The protective pattern comprises a first element separation region formed on the semiconductor substrate, a second element separation region formed on the semiconductor substrate and having a width smaller than that of the first element separation region, a first element region formed between the first element separation region and the second element separation region, a first gate layer formed on the first element separation region, a wiring layer formed on the first gate layer, a passivation layer formed above the wiring layer, a second element region, an insulation film formed on the second element region, and a second gate layer formed on the insulation film, the first element separation region, the first element region, the second element separation region and the second element region being located in this order from the nearer side of the circuit element region.

摘要翻译： 半导体器件具有形成在半导体衬底上的电路元件区域和形成为围绕电路元件区域的保护图案。 保护图案包括形成在半导体衬底上的第一元件分离区域，形成在半导体衬底上的第二元件分离区域，其宽度小于第一元件分离区域的宽度;第一元素区域，形成在第一元素分离区域 和第二元件分离区域，形成在第一元件分离区域上的第一栅极层，形成在第一栅极层上的布线层，形成在布线层上方的钝化层，第二元素区域，形成在第二栅极层上的绝缘膜 元件区域和形成在绝缘膜上的第二栅极层，第一元件分离区域，第一元件区域，第二元件分离区域和第二元件区域从电路元件区域的更靠近的方向定位。

公开(公告)号：US5834835A

公开(公告)日：1998-11-10

申请号：US634678

申请日：1996-04-18

申请人： Hideaki Maekawa

发明人： Hideaki Maekawa

IPC分类号： H01L21/60 ,  H01L21/54 ,  H01L23/08 ,  H01L23/13 ,  H01L23/24 ,  H01L23/02 ,  H01L23/495

CPC分类号： H01L23/13 ,  H01L21/54 ,  H01L23/24 ,  H01L2224/05554 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/49175 ,  H01L2224/73265 ,  H01L2224/83192 ,  H01L2224/92247 ,  H01L24/48 ,  H01L24/49 ,  H01L2924/00014 ,  H01L2924/07802 ,  H01L2924/15151 ,  H01L2924/15153 ,  H01L2924/15165

摘要： In the semiconductor of the present invention, the first pair of pad lines consisting of a plurality of pads are arranged on the bottom portion of the recess portion of the enclosure, the recess portion being made at the center portion of the enclosure by the counterboring process to have a predetermined depth. At approximately center of the recess portion, a suction opening is made so as to suck the potting material from outside. In the recess portion of the enclosure, the semiconductor chip is supported. The semiconductor chip has the second pair of pad lines arranged to oppose to the first pair of pad lines and electrically connected to the first pair of pad lines respectively. The potting material is poured into the recess portion so as to completely cover the semiconductor chip. At the same time, the potting material is sucked from the suction opening.

摘要翻译： 在本发明的半导体中，由多个焊盘组成的第一对焊盘线布置在外壳的凹部的底部，凹部通过安装工艺制成在外壳的中心部分 具有预定的深度。 在凹部的大致中央部，形成吸入口，从外部吸入灌封材料。 在外壳的凹部中，支撑半导体芯片。 半导体芯片具有与第一对焊盘线相对配置的第二对焊盘线，并分别与第一对焊盘线电连接。 将灌封材料注入凹部，以完全覆盖半导体芯片。 同时，灌封材料从吸入口吸入。

公开(公告)号：US5134060A

公开(公告)日：1992-07-28

申请号：US525445

申请日：1990-05-18

申请人： Hideaki Maekawa ,  Makoto Kajiwara ,  Masanobu Miyoshi ,  Mitsuhiro Okumura

发明人： Hideaki Maekawa ,  Makoto Kajiwara ,  Masanobu Miyoshi ,  Mitsuhiro Okumura

IPC分类号： G03C1/08 ,  G03C1/015 ,  G03C1/035 ,  G03C1/09 ,  G03C1/34

CPC分类号： G03C1/09 ,  G03C1/015 ,  G03C1/346 ,  G03C2001/03517

摘要： A silver halide photographic emulsion containing silver halide grains having a silver chloride content of not less than 90 mol % and a method for preparing thereof are disclosed, wherein the silver halide grains are obtained by forming said silver halide grains in the presence of a water-soluble iridium compound and a nitrogen-containing heterocyclic compound capable of forming sparingly-soluble silver salt; and by controlling the addition of said iridium compound, whereby the photographic emulsion is improved in the dependence of gradation on exposure intensity.

公开(公告)号：US08525249B2

公开(公告)日：2013-09-03

申请号：US13301136

申请日：2011-11-21

申请人： Hideaki Maekawa

发明人： Hideaki Maekawa

IPC分类号： H01L29/788

CPC分类号： H01L29/06 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11524 ,  H01L29/7881 ,  Y10S438/926

摘要： A semiconductor memory includes a memory cell array area provided with first and second memory cells and having a first active area and a first element isolation area constituting a line & space structure, and having a floating gate electrode and a control gate electrode in the first active area, a word line contact area adjacent to the memory cell array area and having a second active area, first and second word lines with a metal silicide structure, functioning respectively as the control gate electrodes of the first and second memory cells and arranged to straddle the memory cell array area and the word line contact area. A dummy gate electrode is arranged just below the first and second word lines in the second active area.

摘要翻译： 半导体存储器包括具有第一和第二存储单元的存储单元阵列区域，并且具有构成线和空间结构的第一有源区和第一元件隔离区，并且在第一有源区中具有浮置栅电极和控制栅电极 区域，与存储单元阵列区域相邻并具有第二有效区域的字线接触区域，具有金属硅化物结构的第一和第二字线分别用作第一和第二存储器单元的控制栅电极并且被布置成跨越 存储单元阵列区域和字线接触区域。 虚拟栅极布置在第二有源区域中的第一和第二字线的正下方。

公开(公告)号：US20120020158A1

公开(公告)日：2012-01-26

申请号：US13187000

申请日：2011-07-20

申请人： Tohru OZAKI ,  Mitsuhiro Noguchi ,  Hideaki Maekawa ,  Hiromitsu Mashita ,  Takafumi Taguchi ,  Kazuhito Kobayashi ,  Hidefumi Mukai ,  Hiroyuki Nitta

发明人： Tohru OZAKI ,  Mitsuhiro Noguchi ,  Hideaki Maekawa ,  Hiromitsu Mashita ,  Takafumi Taguchi ,  Kazuhito Kobayashi ,  Hidefumi Mukai ,  Hiroyuki Nitta

IPC分类号： G11C16/04 ,  H01L21/78

CPC分类号： H01L27/11521

摘要： A memory cell array includes memory strings arranged in a first direction. Word-lines and select gate lines extend in a second direction perpendicular to the first direction. The select gate line also extends in the second direction. The word-lines have a first line width in the first direction and arranged with a first distance therebetween. The select gate line includes a first interconnection in the first direction, the first interconnection having a second line width larger than the first line width, and a second interconnection extending from an end portion of the first interconnection, the second interconnection having a third line width the same as the first line width. A first word-line adjacent to the select gate line is arranged having a second distance to the second interconnection, the second distance being (4N+1) times the first distance (N being an integer of 1 or more).

摘要翻译： 存储单元阵列包括沿第一方向布置的存储器串。 字线和选择栅极线在垂直于第一方向的第二方向上延伸。 选择栅极线也沿第二方向延伸。 字线在第一方向上具有第一线宽度并且以它们之间的第一距离布置。 选择栅极线包括在第一方向上的第一互连，第一互连具有大于第一线宽的第二线宽，以及从第一互连的端部延伸的第二互连，第二互连具有第三线宽 与第一行宽度相同。 与选择栅极线相邻的第一字线布置成具有到第二互连的第二距离，第二距离为（4N + 1）倍于第一距离（N为1或更大的整数）。

公开(公告)号：US5070008A

公开(公告)日：1991-12-03

申请号：US614019

申请日：1990-11-14

申请人： Hideaki Maekawa ,  Masanobu Miyoshi

发明人： Hideaki Maekawa ,  Masanobu Miyoshi

IPC分类号： G03C1/015

CPC分类号： G03C1/015 ,  G03C2001/03517 ,  G03C2001/03558

摘要： A light-sensitive silver halide photographic material which comprises a support and provided thereon a silver halide emulsion layer containing silver halide grains of which silver chloride content is not less than 90 mol %, and which have been formed in the presence of an iridium compound and a nitrogen containing heterocyclic compound, and under acidic condition is disclosed.

摘要翻译： 一种感光卤化银照相材料，其包含载体并在其上提供含卤化银颗粒的卤化银乳剂层，其中氯化银含量不小于90mol％，并且在铱化合物存在下形成， 含氮杂环化合物，并且在酸性条件下。

公开(公告)号：US07948021B2

公开(公告)日：2011-05-24

申请号：US12108101

申请日：2008-04-23

申请人： Hideaki Maekawa

发明人： Hideaki Maekawa

IPC分类号： H01L29/788

CPC分类号： H01L29/06 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11524 ,  H01L29/7881 ,  Y10S438/926

摘要： A semiconductor memory includes a memory cell array area provided with first and second memory cells and having a first active area and a first element isolation area constituting a line & space structure, and having a floating gate electrode and a control gate electrode in the first active area, a word line contact area adjacent to the memory cell array area and having a second active area, first and second word lines with a metal silicide structure, functioning respectively as the control gate electrodes of the first and second memory cells and arranged to straddle the memory cell array area and the word line contact area. A dummy gate electrode is arranged just below the first and second word lines in the second active area.

公开(公告)号：US08395205B2

公开(公告)日：2013-03-12

申请号：US13301136

申请日：2011-11-21

申请人： Hideaki Maekawa

发明人： Hideaki Maekawa

IPC分类号： H01L29/788

摘要： A semiconductor memory includes a memory cell array area provided with first and second memory cells and having a first active area and a first element isolation area constituting a line & space structure, and having a floating gate electrode and a control gate electrode in the first active area, a word line contact area adjacent to the memory cell array area and having a second active area, first and second word lines with a metal silicide structure, functioning respectively as the control gate electrodes of the first and second memory cells and arranged to straddle the memory cell array area and the word line contact area. A dummy gate electrode is arranged just below the first and second word lines in the second active area.

公开(公告)号：US08076205B2

公开(公告)日：2011-12-13

申请号：US13081248

申请日：2011-04-06

申请人： Hideaki Maekawa

发明人： Hideaki Maekawa

IPC分类号： H01L21/336

CPC分类号： H01L29/06 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11524 ,  H01L29/7881 ,  Y10S438/926

摘要： A semiconductor memory includes a memory cell array area provided with first and second memory cells and having a first active area and a first element isolation area constituting a line & space structure, and having a floating gate electrode and a control gate electrode in the first active area, a word line contact area adjacent to the memory cell array area and having a second active area, first and second word lines with a metal silicide structure, functioning respectively as the control gate electrodes of the first and second memory cells and arranged to straddle the memory cell array area and the word line contact area. A dummy gate electrode is arranged just below the first and second word lines in the second active area.

摘要翻译： 半导体存储器包括具有第一和第二存储单元的存储单元阵列区域，并且具有构成线和空间结构的第一有源区和第一元件隔离区，并且在第一有源区中具有浮置栅电极和控制栅电极 区域，与存储单元阵列区域相邻并具有第二有效区域的字线接触区域，具有金属硅化物结构的第一和第二字线分别用作第一和第二存储器单元的控制栅电极并且被布置成跨越 存储单元阵列区域和字线接触区域。 虚拟栅极布置在第二有源区域中的第一和第二字线的正下方。