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    Semiconductor memory device comprising a plurality of memory arrays with improved peripheral circuit location and interconnection arrangement
    1.
    发明授权
    Semiconductor memory device comprising a plurality of memory arrays with improved peripheral circuit location and interconnection arrangement 失效
    包含改进的外围电路位置和互连布置的多个存储器阵列的半导体存储器件

    公开(公告)号：US5097440A

    公开(公告)日：1992-03-17

    申请号：US437867

    申请日：1989-11-17

    申请人： Yasuhiro Konishi ,  Masaki Kumanoya ,  Katsumi Dosaka ,  Takahiro Komatsu ,  Yoshinori Inoue

    发明人： Yasuhiro Konishi ,  Masaki Kumanoya ,  Katsumi Dosaka ,  Takahiro Komatsu ,  Yoshinori Inoue

    IPC分类号： G11C11/401 ,  G11C11/4091 ,  G11C11/4097

    CPC分类号： G11C11/4091 ,  G11C11/4097

    摘要： A semiconductor memory device comprises eight memory arrays (b 10a, 10b) arranged in one column. A peripheral circuit (60) is arranged in the central portion of the eight memory arrays (10a, 10b), two column decoders (51, 52) being arranged with the peripheral circuit (60) interposed therebetween. Each of the eight memory arrays (10a, 10b) is provided with a row decoder (20). A plurality of first column selecting lines (CL1) are provided so as to cross the three memory arrays (10a, 10b) arranged on one side of the peripheral circuit (60) from the column decoder (51). In addition, a plurality of second column selecting lines (CL2) are provided so as to intersect with the three memory arrays (10a, 10b) arranged on the other side of the peripheral circuit (60) from the column decoder (52).

    摘要翻译： 半导体存储器件包括布置在一列中的八个存储器阵列（b 10a，10b）。 外围电路（60）布置在八个存储器阵列（10a，10b）的中心部分中，两个列解码器（51,52）被布置在外围电路（60）之间。 八个存储器阵列（10a，10b）中的每一个都具有行解码器（20）。 多列第一列选择线（CL1）被设置为跨越从列解码器（51）排列在外围电路（60）一侧的三个存储器阵列（10a，10b）。 另外，多列第二列选择线（CL2）被设置成与从列解码器（52）配置在外围电路（60）的另一侧的三个存储器阵列（10a，10b）相交。

    Semiconductor memory device comprising a plurality of memory arrays with improved peripheral circuit location and interconnection arrangement
    2.
    发明授权
    Semiconductor memory device comprising a plurality of memory arrays with improved peripheral circuit location and interconnection arrangement 失效
    半导体存储器件包括具有改进的外围电路位置和互连布置的多个存储器阵列

    公开(公告)号：US5184321A

    公开(公告)日：1993-02-02

    申请号：US821875

    申请日：1992-01-16

    申请人： Yasuhiro Konishi ,  Masaki Kumanoya ,  Katsumi Dosaka ,  Takahiro Komatsu ,  Yoshinori Inoue

    发明人： Yasuhiro Konishi ,  Masaki Kumanoya ,  Katsumi Dosaka ,  Takahiro Komatsu ,  Yoshinori Inoue

    IPC分类号： G11C11/4074 ,  G11C11/408

    CPC分类号： G11C11/4074 ,  G11C11/408 ,  Y10S257/92

    摘要： A plurality of memory arrays (10a, 10b) are formed on a semiconductor chip (CH). A peripheral circuit (60) is arranged in the central portion of the plurality of memory arrays (10a, 10b). A plurality of pads (PD;p1.about.p18) are formed on both ends of the semiconductor chip (CH). The plurality of memory arrays (10a, 10b) are formed of predetermined layers (101.about.109). A plurality of interconnections (L) to be connected between the plurality of pads (PD;p1.about.p18) and the peripheral circuit (60) are provided to cross the plurality of memory arrays. The plurality of interconnections (L) are formed of layers (112;113) other than the predetermined ones.

    摘要翻译： 多个存储器阵列（10a，10b）形成在半导体芯片（CH）上。 外围电路（60）布置在多个存储器阵列（10a，10b）的中心部分。 在半导体芯片（CH）的两端形成有多个焊盘（PD; p1差异p18）。 多个存储器阵列（10a，10b）由预定层形成（101差异109）。 要连接在多个焊盘（PD; p1 DIFFERENCE p18）和外围电路（60）之间的多个互连（L）被设置成跨越多个存储器阵列。 多个互连（L）由除预定的互连层之外的层（112; 113）形成。

    Substrate bias generator in a dynamic random access memory with auto/self refresh functions and a method of generating a substrate bias therein
    3.
    发明授权
    Substrate bias generator in a dynamic random access memory with auto/self refresh functions and a method of generating a substrate bias therein 失效
    具有自动/自刷新功能的动态随机存取存储器中的衬底偏置发生器及其中产生衬底偏置的方法

    公开(公告)号：US4961167A

    公开(公告)日：1990-10-02

    申请号：US381347

    申请日：1989-07-18

    申请人： Masaki Kumanoya ,  Yasuhiro Konishi ,  Katsumi Dosaka ,  Takahiro Komatsu ,  Yoshinori Inoue

    发明人： Masaki Kumanoya ,  Yasuhiro Konishi ,  Katsumi Dosaka ,  Takahiro Komatsu ,  Yoshinori Inoue

    IPC分类号： G11C11/4074

    CPC分类号： G11C11/4074

    摘要： A dynamic random access memory with self-refresh function, which includes a substrate bias generator (100) adapted to be intermittently driven to apply a bias potential to a semiconductor substrate (15). This memory device comprises a circuit (91) for generating an internal refresh instruction signal (.phi..sub.S) in response to an external refresh instruction signal, a circuit (92, 93) which, in response to the internal refresh instruction signal, generates a refresh enable signal (.phi..sub.R) intermittently at a predetermined interval, a circuit (94, 95, 96, 98) which, in response to the refresh enable signal, refreshes data in the memory cells, and a circuit (99) which, in response to the internal refresh instruction signal and refresh enable signal, activates the substrate bias generator in the same cycle as the cycle of generation of the refresh enable signal and only for a time shorter than the cycle of generation of the refresh enable signal. The above construction contributes to a reduced power consumption in the dynamic random access memory.

    摘要翻译： 一种具有自刷新功能的动态随机存取存储器，其包括适于被间歇地驱动以向半导体衬底（15）施加偏置电位的衬底偏置发生器（100）。 该存储装置包括用于响应于外部刷新指令信号产生内部刷新指令信号（phi S）的电路（91），响应于内部刷新指令信号产生刷新的电路（92,93） 使能信号（phi R）以预定的间隔间歇地连接到响应于刷新使能信号刷新存储器单元中的数据的电路（94,95,96,98）和响应于电路（99）的电路（99） 对于内部刷新指令信号和刷新使能信号，在与产生刷新使能信号的周期相同的周期中，仅在比生成刷新使能信号的周期短的时间内激活衬底偏置发生器。 上述结构有助于动态随机存取存储器中的功耗降低。

    Dynamic-type semiconductor memory device operable in test mode and method of testing functions thereof
    4.
    发明授权
    Dynamic-type semiconductor memory device operable in test mode and method of testing functions thereof 失效
    在测试模式下可操作的动态半导体存储器件及其功能的测试方法

    公开(公告)号：US5208778A

    公开(公告)日：1993-05-04

    申请号：US739736

    申请日：1991-07-30

    申请人： Masaki Kumanoya ,  Katsumi Dosaka ,  Yasuhiro Konishi ,  Takahiro Komatsu ,  Yoshinori Inoue

    发明人： Masaki Kumanoya ,  Katsumi Dosaka ,  Yasuhiro Konishi ,  Takahiro Komatsu ,  Yoshinori Inoue

    IPC分类号： G11C29/36

    CPC分类号： G11C29/36

    摘要： A dynamic-type semiconductor memory device has a test mode of simultaneously carrying out functional testing on a plurality of bits of memory cells. In data writing in the test mode, data inverted from the write-in data is written in at least a 1-bit memory cell out of the plurality of bits of memory cells selected simultaneously, and the same data as the write-in data is written in the remaining memory cells. In data reading in the test mode, the data of those of the memory cells selected simultaneously, in which the inverted data is written are inverted and read, while the data of the remaining memory cells are read as they are. Logic processing is carried out on the read-out data of the plurality of bits, so that a logic value indicating acceptability of the semiconductor memory device is output, depending on a result of determination as to whether or not the read-out data is the same as each other.

    摘要翻译： 动态型半导体存储器件具有在多个位的存储单元上同时执行功能测试的测试模式。 在测试模式下的数据写入中，从写入数据反转的数据被写入到同时选择的多个存储单元中的至少1位存储单元中，与写入数据相同的数据是 写在剩余的存储单元中。 在测试模式下的数据读取中，将反转数据写入的同时选择的存储单元的数据进行反转和读取，而剩余存储单元的数据原样读取。 对多个位的读出数据执行逻辑处理，从而根据关于读出的数据是否为0的确定结果输出表示半导体存储器件的可接受性的逻辑值 相同。

    Semiconductor memory device having shared sense amplifier and operating method thereof
    5.
    发明授权
    Semiconductor memory device having shared sense amplifier and operating method thereof 失效
    具有共享读出放大器的半导体存储器件及其操作方法

    公开(公告)号：US5014246A

    公开(公告)日：1991-05-07

    申请号：US435901

    申请日：1989-11-14

    申请人： Takahiro Komatsu ,  Masaki Kumanoya ,  Yasuhiro Konishi ,  Katsumi Dosaka ,  Yoshinori Inoue

    发明人： Takahiro Komatsu ,  Masaki Kumanoya ,  Yasuhiro Konishi ,  Katsumi Dosaka ,  Yoshinori Inoue

    IPC分类号： G11C11/401 ,  G11C11/409 ,  G11C11/4091

    CPC分类号： G11C11/4091

    摘要： A memory cell array (10) is divided into four blocks. Each block comprises a memory cell array block (10aand a memory cell array block (10b). A sense amplifier block (20) is disposed between the memory cell array blocks (10a) and (10b). Each sense amplifier block (20) is connected to the memory cell array blocks (10a) and (10b) via switching circuits (80a, 80b), respectively. Four decoders (51) are provided corresponding to the four blocks. The four decoders (51) are commonly provided with a driver (52) generating a high level driving signal. Each decoder (51) is responsive to an address signal for supplying a driving signal from the driver (52) to either one of the switching circuits (80a, 80b) and for applying a ground potential to the other one of the circuits. Accordingly, the sense amplifier block (20) is connected to either one of the memory cell array blocks (10a, 10b ).

    摘要翻译： 存储单元阵列（10）被分成四个块。 每个块包括存储单元阵列块（10a和存储单元阵列块），读出放大器块（20）设置在存储单元阵列块（10a）和（10b）之间，每个读出放大器块（20）是 分别经由开关电路（80a，80b）连接到存储单元阵列块（10a）和（10b），四个解码器（51）分别对应于四个块，四个解码器（51）通常配置有驱动器 （52）产生高电平驱动信号，每个解码器（51）响应于地址信号，用于将来自驱动器（52）的驱动信号提供给开关电路（80a，80b）中的任一个并且用于施加地电位 因此，读出放大器块（20）连接到存储单元阵列块（10a，10b）中的任意一个。

    Voltage boosting circuit and operating method thereof
    6.
    发明授权
    Voltage boosting circuit and operating method thereof 失效
    升压电路及其工作方法

    公开(公告)号：US5010259A

    公开(公告)日：1991-04-23

    申请号：US454580

    申请日：1989-12-21

    申请人： Yoshinori Inoue ,  Masaki Kumanoya ,  Takahiro Komatsu ,  Yasuhiro Konishi ,  Katsumi Dosaka

    发明人： Yoshinori Inoue ,  Masaki Kumanoya ,  Takahiro Komatsu ,  Yasuhiro Konishi ,  Katsumi Dosaka

    IPC分类号： G11C11/407 ,  H01L21/822 ,  H01L21/8242 ,  H01L27/04 ,  H01L27/10 ,  H01L27/108 ,  H02M3/07 ,  H03K5/02 ,  H03K19/017 ,  H03K19/094

    CPC分类号： H03K19/01714

    摘要： An input signal is inverted by a CMOS inverter and provided for an output signal line. The CMOS inverter is provided between a power supply and a ground, and its node on the side of the power supply is charged all the time to prevent the potential thereof from being lowered. An output signal provided for the output signal line is delayed by a delay circuit to be applied to a boosting capacitor. The potential of the node is further boosted by this boosting capacitor. Consequently, the potential of the output signal is also boosted. When the potential of the node is raised higher than a supply voltage, an N channel MOSFET for charging is turned off to prevent a reverse flow of a charge.

    摘要翻译： 输入信号由CMOS反相器反相并提供给输出信号线。 CMOS反相器设置在电源和地之间，并且其电源侧的节点一直被充电以防止其电位降低。 为输出信号线提供的输出信号被延迟电路延迟以施加到升压电容器。 该升压电容器进一步提升了节点的电位。 因此，输出信号的电位也得到提升。 当节点的电位升高到高于电​​源电压时，用于充电的N沟道MOSFET关闭，以防止电荷反向流动。

    Substrate bias potential generator of a semiconductor integrated circuit device and a generating method therefor
    8.
    发明授权
    Substrate bias potential generator of a semiconductor integrated circuit device and a generating method therefor 失效
    半导体集成电路器件的衬底偏置电位发生器及其生成方法

    公开(公告)号：US4961007A

    公开(公告)日：1990-10-02

    申请号：US337218

    申请日：1989-04-12

    申请人： Masaki Kumanoya ,  Yasuhiro Konishi ,  Katsumi Dosaka ,  Takahiro Komatsu ,  Youichi Tobita

    发明人： Masaki Kumanoya ,  Yasuhiro Konishi ,  Katsumi Dosaka ,  Takahiro Komatsu ,  Youichi Tobita

    IPC分类号： G11C11/408 ,  G05F3/20 ,  H01L21/822 ,  H01L21/8242 ,  H01L27/04 ,  H01L27/10 ,  H01L27/108

    CPC分类号： G05F3/205 ,  H02M3/07

    摘要： A substrate bias potential generator for biasing a semiconductor substrate to a predetermined potential includes first and second substrate bias generating circuits which operate alternatively according to the potential of the substrate, whereby consumption of power in the substrate bias potential generator is reduced. The alternative operation of the bias generating circuits each activated by a pulse signal train is performed by using a first insulated gate transistor having a gate electrode connected to the semiconductor substrate, a second insulated gate transistor having a gate electrode for receiving the reference potential, an amplifier for differentially amplifying outputs of the first and second insulated gate transistors, an insulated gate transistor for charging an output of the amplifier to a predetermined potential when the amplifier is activated, and a circuit for transmitting the output of the differential amplifier to the first and second bias potential generating circuits. The differential amplifier is activated in response to an activation signal of a pulse train whereby an activation signal corresponding to the pulse train is transmitted to either substrate bias potential generating circuit.

    摘要翻译： 用于将半导体衬底偏置到预定电位的衬底偏置电位发生器包括根据衬底的电位交替地操作的第一和第二衬底偏置产生电路，由此降低衬底偏置电位发生器中的功率消耗。 通过使用具有连接到半导体衬底的栅电极的第一绝缘栅极晶体管，具有用于接收参考电位的栅电极的第二绝缘栅极晶体管，执行由脉冲信号列激活的偏置产生电路的替代操作， 放大器，用于差分放大第一和第二绝缘栅极晶体管的输出;绝缘栅极晶体管，用于在放大器被激活时将放大器的输出充电到预定电位;以及电路，用于将差分放大器的输出传输到第一和第二绝缘栅极晶体管， 第二偏置电位发生电路。 差分放大器响应于脉冲串的激活信号被激活，由此将对应于脉冲串的激活信号传输到任一衬底偏置电位产生电路。