公开(公告)号：US4933907A

公开(公告)日：1990-06-12

申请号：US278552

申请日：1988-12-01

申请人： Masaki Kumanoya ,  Katsumi Dosaka ,  Yasuhiro Konishi ,  Hiroyuki Yamasaki ,  Takahiro Komatsu ,  Yoichi Tobita

发明人： Masaki Kumanoya ,  Katsumi Dosaka ,  Yasuhiro Konishi ,  Hiroyuki Yamasaki ,  Takahiro Komatsu ,  Yoichi Tobita

IPC分类号： G11C11/406

CPC分类号： G11C11/40615 ,  G11C11/406

摘要： A dynamic random access memory having a self-refresh mode comprises a memory array partitioned into four groups in which control are respectively performed and a partial activation control circuit. The four groups in the memory array are alternately refreshed two by two in an operation under the self-refresh mode. As a result, each group in the memory array is refreshed at a time interval of two times a conventional refresh interval, so that the power consumption is decreased.

摘要翻译： 具有自刷新模式的动态随机存取存储器包括分为四组的存储器阵列，其中分别执行控制和部分激活控制电路。 存储器阵列中的四组在自刷新模式下的操作中被两个两个地刷新。 结果，存储器阵列中的每个组以传统刷新间隔的两倍的时间间隔被刷新，使得功耗降低。

公开(公告)号：US4984206A

公开(公告)日：1991-01-08

申请号：US372441

申请日：1989-06-27

申请人： Takahiro Komatsu ,  Hiroyuki Yamasaki ,  Katsumi Dosaka ,  Yoichi Tobita

发明人： Takahiro Komatsu ,  Hiroyuki Yamasaki ,  Katsumi Dosaka ,  Yoichi Tobita

IPC分类号： G11C11/409 ,  G11C7/00 ,  G11C7/06 ,  G11C7/10

CPC分类号： G11C7/1069 ,  G11C7/00 ,  G11C7/062 ,  G11C7/065 ,  G11C7/1006 ,  G11C7/1051 ,  G11C7/1078

摘要： A dynamic random access memory comprises a pair of write-in data transferring lines (IL, IL), a pair of read-out data transferring lines (OL, OL) and a current-mirror type sense amplifier comprising (30) CMOS transistors. The current-mirror type amplifier (30) is connected between a plurality of bit line pairs (BL, BL) and the pair of read-out data transferring lines (OL, OL). At the time of data reading, the pair of write-in data transferring lines (IL, IL) is connected to the corresponding bit line pair (BL, BL) in response to a write-in column decoded signal (YW) obtained by ANDing a column decoded signal (CA) with a write-in instruction signal (W).

摘要翻译： 动态随机存取存储器包括一对写入数据传输线（IL，＆amp; Upbar＆I），一对读出数据传输线（OL，＆amp; upbar＆O）和电流镜型读出放大器，包括（30）CMOS 晶体管。 电流镜式放大器（30）连接在多个位线对（BL，＆amp; B和B）与一对读出数据传输线（OL，＆amp; upbar＆O）之间。 在数据读取时，响应于获得的写入列解码信号（YW），一对写入数据传输线（IL，＆amp; upbar＆I）被连接到对应的位线对（BL，＆amp; B和B） 通过将列解码信号（CA）与写入指令信号（W）进行AND运算。

公开(公告)号：US4670706A

公开(公告)日：1987-06-02

申请号：US824830

申请日：1986-01-31

申请人： Yoichi Tobita

发明人： Yoichi Tobita

IPC分类号： G05F1/618 ,  G05F1/20 ,  G05F1/56 ,  G05F3/24 ,  G11C11/407 ,  G05F3/20

CPC分类号： G05F3/24

摘要： In a constant voltage generating circuit, a predetermined voltage outputted by voltage applying means connected between first and second power source terminals is simultaneously applied to the control electrode of a first MOS transistor of a first polarity and the control electrode of a second MOS transistor of a second polarity which are provided complementarily, and a voltage obtained by subtracting the threshold voltage of the first MOS transistor from the potential at the control electrode of the first MOS transistor is applied to the control electrode of a third MOS transistor of the second polarity while a voltage obtained by adding the potential at the control electrode of the second MOS transistor to the threshold voltage of the second MOS transistor is applied to a fourth MOS transistor of the first polarity, so that each of the third and fourth MOS transistors is operated in the critical state between the conductive state and the non-conductive state, whereby positive or negative noise voltage included in the output voltage of the circuit is quickly eliminated.

摘要翻译： 在恒压发生电路中，连接在第一和第二电源端子之间的电压施加装置输出的预定电压同时施加到第一极性的第一MOS晶体管的控制电极和第一极性的第二MOS晶体管的控制电极 第二极性，并且通过从第一MOS晶体管的控制电极处的电位减去第一MOS晶体管的阈值电压而获得的电压被施加到第二极性的第三MOS晶体管的控制电极，而 将第二MOS晶体管的控制电极上的电位加上第二MOS晶体管的阈值电压而获得的电压施加到第一极性的第四MOS晶体管，使得第三和第四MOS晶体管中的每一个在 导通状态与非导通状态之间的临界状态，由此正或负 快速消除电路输出电压中包含的噪声电压。

公开(公告)号：US5490116A

公开(公告)日：1996-02-06

申请号：US151248

申请日：1993-11-12

申请人： Yoichi Tobita ,  Kenji Tokami

发明人： Yoichi Tobita ,  Kenji Tokami

IPC分类号： G11C11/407 ,  G11C8/08 ,  G11C8/18 ,  G11C11/408 ,  H01L21/822 ,  H01L21/8242 ,  H01L27/02 ,  H01L27/04 ,  H01L27/10 ,  H01L27/108 ,  G11C7/00

CPC分类号： G11C11/4085 ,  G11C8/08 ,  G11C8/18 ,  H01L27/0218 ,  H01L2924/0002

摘要： In a semiconductor memory device including a boosting circuit for generating a high voltage constantly, and a word line driving circuit for transmitting a high voltage from the boosting circuit on a selected word line, a capacitor for stabilizing the high voltage generated by the boosting circuit is formed of a series of capacitive elements using a FET having a gate insulating film identical in thickness to that of a insulating gate type field effect transistor in the memory device. A voltage applied across each capacitive element is relaxed, and the capacitor is improved in dielectric breakdown voltage characteristics, to stably supply the high voltage.

摘要翻译： 在包括用于恒定地产生高电压的升压电路的半导体存储器件和用于在选定字线上从升压电路传输高电压的字线驱动电路，用于稳定由升压电路产生的高电压的电容器是 由使用具有与绝缘栅型场效应晶体管的厚度相同的栅极绝缘膜的FET的一系列电容元件形成在存储器件中。 施加在每个电容元件上的电压被松弛，并且电容器的介电击穿电压特性得到改善，以稳定地提供高电压。

公开(公告)号：US5051995A

公开(公告)日：1991-09-24

申请号：US302034

申请日：1989-01-26

申请人： Yoichi Tobita

发明人： Yoichi Tobita

IPC分类号： G11C29/46 ,  G11C29/50

CPC分类号： G11C29/028 ,  G11C29/46 ,  G11C29/50 ,  G11C11/401 ,  G11C2029/5004

摘要： In a semiconductor memory device having a test mode setting circuit, when a voltage higher than a common operation range is applied to an input terminal (101) receiving CAS signals, a first voltage detecting circuit (100) detects the voltage and the detected output is latched in a latch circuit (110). A voltage setting circuit (1 20) sets a cell plate voltage of a memory cell (1a) approximately at the ground potential in response to the latch output. Consequently, the operation margin of the memory cell for the data "1" can be carried out by the V bump test. Meanwhile, when a voltage higher than the normal operation range is applied to an input terminal (201) receiving WE signals, a second voltage detecting circuit (200) detects the voltage and the detected output is latched in the latch circuit (201). The voltage setting circuit sets the cell plate voltage approximately at Vcc in response to the latch output from the latch circuit.

摘要翻译： 在具有测试模式设置电路的半导体存储器件中，当将高于公共操作范围的电压施加到接收和上行＆amp; C信号的输入端（101）时，第一电压检测电路（100）检测电压和检测到的输出 被锁存在锁存电路（110）中。 响应于锁存输出，电压设定电路（120）将存储单元（1a）的单元板电压大致设置在接地电位。 因此，数据“1”的存储单元的操作余量可以通过V凸块测试来执行。 同时，当对接收＆amp; W信号的输入端子（201）施加高于正常工作范围的电压时，第二电压检测电路（200）检测电压，检测出的输出被锁存在锁存电路（201）中。 电压设定电路响应于来自锁存电路的锁存器输出将单元板电压设置为大致Vcc。

公开(公告)号：US5892390A

公开(公告)日：1999-04-06

申请号：US971572

申请日：1997-11-17

申请人： Yoichi Tobita

发明人： Yoichi Tobita

IPC分类号： G05F3/24 ,  G05F1/46 ,  G11C5/14 ,  G11C11/407 ,  H02J1/04 ,  G05F3/02

CPC分类号： G05F1/465

摘要： An internal power supply circuit includes a first output MOS transistor for transmitting a first reference voltage in a source follower mode, an internal reference voltage generating circuit for generating a second reference voltage from the output voltage of the first MOS transistor, and an output MOS transistor coupled between a power supply node and an output node and operating in the source follower mode in accordance with the second internal reference voltage. Internal reference voltage generating circuit has a function of canceling an influence of the threshold voltages of output MOS transistor and the first MOS transistor on the internal voltage VINT on the output node. Since comparing circuit for comparing the internal voltage and the reference voltage is not used, current consumption necessary for the comparing operation can be reduced.

摘要翻译： 内部电源电路包括用于发送源极跟随器模式中的第一参考电压的第一输出MOS晶体管，用于从第一MOS晶体管的输出电压产生第二参考电压的内部参考电压产生电路，以及输出MOS晶体管 耦合在电源节点和输出节点之间，并且根据第二内部参考电压在源跟随器模式下工作。 内部参考电压产生电路具有消除输出MOS晶体管和第一MOS晶体管的阈值电压对输出节点上的内部电压VINT的影响的功能。 由于不使用用于比较内部电压和参考电压的比较电路，因此可以减少比较操作所需的电流消耗。

公开(公告)号：USRE35645E

公开(公告)日：1997-10-28

申请号：US39660

申请日：1993-03-30

申请人： Yoichi Tobita

发明人： Yoichi Tobita

IPC分类号： G11C29/46 ,  G11C29/50 ,  G11C29/00

CPC分类号： G11C29/028 ,  G11C29/46 ,  G11C29/50 ,  G11C11/401 ,  G11C2029/5004

摘要： In a semiconductor memory device having a test mode setting circuit, when a voltage higher than a common operation range is applied to an input terminal (101) receiving CAS signals, a first voltage detecting circuit (100) detects the voltage and the detected output is latched in a latch circuit (110). A voltage setting circuit .�.(1 20).!. .Iadd.(120) .Iaddend.sets a cell plate voltage of a memory cell .�.(1a).!. .Iadd.(1) .Iaddend.approximately at the ground potential in response to the latch output. Consequently, the operation margin of the memory cell for the data "1" can be carried out by the V bump test. Meanwhile, when a voltage higher than the normal operation range is applied to an input terminal (201) receiving WE signals, a second voltage detecting circuit (200) detects the voltage and the detected output is latched in the latch circuit .�.(201).!..Iadd.(210).Iaddend.. The voltage setting circuit sets the cell plate voltage approximately at Vcc in response to the latch output from the latch circuit.

摘要翻译： 在具有测试模式设置电路的半导体存储器件中，当对接收+ E，ovs CAS + EE信号的输入端子（101）施加高于公共操作范围的电压时，第一电压检测电路（100）检测 并且检测到的输出被锁存在锁存电路（110）中。 响应于锁存输出，电压设定电路[（120）]（120）将存储单元[（1a）]（1）的单元板电压大致设置在接地电位。 因此，数据“1”的存储单元的操作余量可以通过V凸块测试来执行。 同时，当对接收+ E，ovs WE + EE信号的输入端子（201）施加高于正常工作范围的电压时，第二电压检测电路（200）检测电压，检测到的输出被锁存在锁存器 电路[（201）]（210）。 电压设定电路响应于来自锁存电路的锁存器输出将单元板电压设置为大致Vcc。

公开(公告)号：USRE34290E

公开(公告)日：1993-06-22

申请号：US735129

申请日：1991-07-24

申请人： Yoichi Tobita

发明人： Yoichi Tobita

IPC分类号： G05F1/618 ,  G05F1/20 ,  G05F1/56 ,  G05F3/24 ,  G11C11/407

CPC分类号： G05F3/24

摘要： In a constant voltage generating circuit, a predetermined voltage outputted by voltage applying means connected between first and second power source terminals is simultaneously applied to the control electrode of a first MOS transistor of a first polarity and the control electrode of a second MOS transistor of a second polarity which are provided complementarily, and a voltage obtained by subtracting the threshold voltage of the first MOS transistor from the potential at the control electrode of the first MOS transistor is applied to the control electrode of a third MOS transistor of the second polarity while a voltage obtained by adding the potential at the control electrode of the second MOS transistor to the threshold voltage of the second MOS transistor is applied to a fourth MOS transistor of the first polarity, so that each of the third and fourth MOS transistors is operated in the critical state between the conductive state and the non-conductive state, whereby positive or negative noise voltage included in the output voltage of the circuit is quickly eliminated.This is a Reissue of a Patent which was the subject of a Reexamination Certificate No. B1 4,670,706, dated Jul. 25, 1989, Request No. 90/001689.

公开(公告)号：US5646516A

公开(公告)日：1997-07-08

申请号：US522439

申请日：1995-08-31

申请人： Yoichi Tobita

发明人： Yoichi Tobita

IPC分类号： H01L27/04 ,  G05F3/24 ,  G05F3/26 ,  G11C11/407 ,  H01L21/822 ,  G05F3/16

CPC分类号： G05F3/247

摘要： An MOS transistor Q3 operates in a diode mode, and applies a voltage which is lower than a power supply voltage Vcc by an absolute value of its threshold voltage to the gate of an MOS transistor Q1. MOS transistor Q1 operates in a saturation region, and a supplies current which is in proportion to the difference between the threshold voltages of MOS transistors Q3 and Q1 to an output node 2. An MOS transistor Q4 also operates in a diode mode and applies a voltage equal to its threshold voltage to the gate of MOS transistor Q2. MOS transistor Q2 operates in a saturation region, and discharges current which is in proportion to the difference between the gate-source voltage and the threshold voltage. The currents flowing through MOS transistor Q1 and through MOS transistor Q2 are equal to each other. Accordingly, the dependency upon temperature of the threshold voltages is canceled, and thus an output voltage V0 with extremely low dependency upon temperature can be obtained at output node 2. A circuit which generates a reference voltage with no dependency upon power supply voltage and extremely low dependency upon temperature is provided.

摘要翻译： MOS晶体管Q3以二极管模式工作，并且向MOS晶体管Q1的栅极施加低于电源电压Vcc的阈值电压的绝对值的电压。 MOS晶体管Q1在饱和区域中工作，并且将与MOS晶体管Q3和Q1的阈值电压之间的差成比例的电流提供给输出节点2.MOS晶体管Q4还以二极管模式工作，并施加电压 等于其对MOS晶体管Q2的栅极的阈值电压。 MOS晶体管Q2在饱和区域中工作，并且放电与栅源电压和阈值电压之间的差成比例的电流。 流过MOS晶体管Q1和MOS晶体管Q2的电流彼此相等。 因此，阈值电压对温度的依赖性被消除，因此在输出节点2处可以获得对温度依赖性非常低的输出电压V0。产生不依赖于电源电压且极低的参考电压的电路 提供了对温度的依赖。

公开(公告)号：US5544102A

公开(公告)日：1996-08-06

申请号：US471047

申请日：1995-06-06

申请人： Yoichi Tobita ,  Kenji Tokami

发明人： Yoichi Tobita ,  Kenji Tokami

IPC分类号： G11C11/407 ,  G11C8/08 ,  G11C8/18 ,  G11C11/408 ,  H01L21/822 ,  H01L21/8242 ,  H01L27/02 ,  H01L27/04 ,  H01L27/10 ,  H01L27/108 ,  G11C7/00

CPC分类号： G11C11/4085 ,  G11C8/08 ,  G11C8/18 ,  H01L27/0218 ,  H01L2924/0002

摘要： In a semiconductor memory device including a boosting circuit for generating a high voltage constantly, and a word line driving circuit for transmitting a high voltage from the boosting circuit on a selected word line, a capacitor for stabilizing the high voltage generated by the boosting circuit is formed of a series of capacitive elements using a FET having a gate insulating film identical in thickness to that of a insulating gate type field effect transistor in the memory device. A voltage applied across each capacitive element is relaxed, and the capacitor is improved in dielectric breakdown voltage characteristics, to stably supply the high voltage.

摘要翻译： 在包括用于恒定地产生高电压的升压电路的半导体存储器件和用于在选定字线上从升压电路传输高电压的字线驱动电路，用于稳定由升压电路产生的高电压的电容器是 由使用具有与绝缘栅型场效应晶体管的厚度相同的栅极绝缘膜的FET的一系列电容元件形成在存储器件中。 施加在每个电容元件上的电压被松弛，并且电容器的介电击穿电压特性得到改善，以稳定地提供高电压。